This section describes the necessary changes needed if you want to reuse a general project that was created based on projects in LabVIEW Communications 2.0. For details specific to USRP or the Application Frameworks, refer to those sections.
This section includes the following parts:
Projects Containing Multiple FPGA Targets
It is generally recommended that project migration should be limited to a single target at a time to reduce complexity and to make migration efforts easier. If a project does contain multiple targets, there may be issues if the same resource name is shared between these targets. For example, top-level VIs, subVIs, or common resource names that are shared between targets. To address this, remove all but one of the targets, migrate, and, if necessary, add the additional targets back into the newer project. Additionally, any broken VIs must be fixed by manually selecting the correct FPGA resources.
579x Sample Clock
Projects using 579x targets will have broken VIs that reference the “Sample Clock”. This clock has been renamed to the “Data Clock” and must be reconfigured.
For additional details, or information on migrating one of the NI-579xR streaming projects, see the FlexRIO Projects topic.
Reconfigure Xixlinx IP
Xilinx IP needs to be reconfigured due to the new Vivado version used in LabVIEW Communications 2.0.
To find the affected files and make the necessary updates, follow these steps:
- Open the FPGA top-level you wish to migrate.
- Wait until type propagation has occurred.
- Once the document finishes loading, you will see in the list of errors the affected files, as shown in Figure 107.
Figure 107: Example error list showing affected files for Xilinx IP Core reconfiguration
- Double-click on the errors as shown in Figure 107. This will open the affected document.
- Select the affected Xilinx IP block, and click Configure Xilinx IP Core in the right-hand rail as shown in Figure 108.
- Wait for the “Re-customize IP“ dialog to appear.
- Inside the “Re-customize IP“ dialog, leave the settings untouched and click OK as shown in Figure 109.
- Wait until the warning “Not Ready“ as shown in Figure 110, has disappeared.
- Repeat steps 2 through 6 until all Errors in the FPGA top-level have disappeared.
Figure 108: How to reconfigure a Xilinx IP Core (1)
Figure 109: How to reconfigure a Xilinx IP Core (2)
Figure 110: "Not Ready" warning because Xilinx tool is processing the IP in the background
The FIFO resource names in the Host VIs which interface with DMA FIFOs must be updated. In LabVIEW Communications 2.0, the FIFO resource contains additional prefixes for the FPGA resource file name along with the FIFO name itself. For example, in the USRP Streaming projects, “Rx Stream 0” becomes “USRP Resources.grsc\Rx Stream 0.” Because of this, all FIFO node instances (Start/Stop, Configure, and Read/Write), along with any FPGA reference terminals, must be updated.
If the host is not updated correctly, runtime errors can occur after migrating over a previous project. These errors may persist even after a recompile in the newer version. A typical error is shown in Figure 111.
Figure 111: Typical Error if Host Not Updated
Note: The bitfile may need to be recompiled in version 2.0 to make use of any changes in resource files that may have been added during migration of the project. This must be done prior to any host-side changes that reference that bitfile.
To update FPGA refnums, complete the following steps:
Note: If the application uses FPGA terminals, or constants, then they may need to be updated to the latest bitfile.
1. Select the FPGA reference and click Configure in the right-hand rail.
Figure 112: Configure Dialog in Right-Hand Rail
- In the “FPGA Interface Dynamic Refnum Configuration“ dialog, click Import bitfile and browse to your recently compiled bitfile.
Note: The default location will be in the <project directory>\Builds folder. However, this, along with the file name, will vary based on the configuration of the build spec used during compile
Figure 113: Import Bitfile
- (Optional) With the “FPGA Interface Dynamic Refnum Configuration“ dialog still open, remove all unused resources by clicking the X symbol on the right side. This will not affect functionality but may make it easier to view used resources at a later time.
- Click OK in the “FPGA Interface Dynamic Refnum“ dialog.
To update DMA FIFO nodes, complete the following steps:
- Select the affected DMA FIFO node.
- In the right-hand rail is a drop-down selection for available FIFO names referenced by the bitfile being used. Select the appropriate resource as shown in Figure 114.
Figure 114: Select Appropriate Resource
Several changes have been made to the USRP API. For a list of these changes, and needed adjustments, see the Host API section under the USRP Projects topic.
USRP 40 MHz
The USRP RIO 40 MHz target will be deprecated in future versions of LabVIEW Communications. Previous projects built for these targets will still be usable in version 2.0 but you should consider migration efforts in future designs. Please see the USRP Projects topic for instructions on how to update to the latest USRP targets.