The electrical architecture specifies the adherence to the PCI, PCI Express, CompactPCI, and CompactPCI Express specifications and power requirements. It also adds specific timing and synchronization features that make the PXI platform unique and suitable for high-performance test and measurement.
The core electrical feature of a PXI chassis is the communication bus. As PCI evolved into PCI Express, the specification has also evolved to ensure PXI can meet even more application needs by integrating PCI Express into the PXI chassis backplane.
For legacy instruments, PXI supports PCI communication—a 32-bit bus commonly used for transmitting and receiving data in parallel. The maximum bandwidth or throughput of a PCI instrument is 132 MB/s. As applications required higher bandwidth, PCI Express was defined where data is sent serially through pairs of transmit and receive connections called lanes, which give data the ability transfer at 250 MB/s per direction. This serial connection is known as a PCI Express Gen1 x1 “link” (by-one). Multiple lanes can be grouped together to form x2, x4, x8, x16, and x32 links to increase bandwidth. These links form a connection between a controller and a slot where an instrument is seated. For example, a x16 slot could transmit and receive 4 GB/s (250 MB/s * 16). To ensure compatibility with previous PXI instruments and new PXI Express instruments, both the PCI and PCI Express communication buses are incorporated into a PXI chassis. As the PCI Express specification evolves to the next generation, PXI will continue to incorporate the new capabilities into a PXI chassis while maintaining backward compatibility.
Figure 7. This example of the NI PXIe-1085 chassis highlights the PCI and PCI Express lines routing to each slot depending on the type of module that the slot accepts.
Along with the chassis communication buses evolving to incorporate the latest PC technology, PXI peripheral modules have evolved from PXI to PXI Express to take advantage of the PCI Express communication bus capabilities. To ensure module compatibility between PXI and PXI Express modules, the PXI specification added the hybrid slot. This slot gives you the ability to insert PXI or PXI Express peripheral modules in PXI chassis. A PXI chassis can include the following:
- A system slot, which accepts an embedded or remote PXI Express controller
- PXI peripheral slots, which accept PXI modules
- PXI Express hybrid peripheral slots, which accept PXI Express peripheral modules, 32-bit CompactPCI peripheral modules, and hybrid-compatible PXI peripheral modules
- A system timing slot, which accepts both PXI Express peripheral modules and PXI Express system timing modules
Figure 8. Slot Types That You Can Find Within a PXI Chassis
To bring it all together, the specification defines the technology that is available through the PXI chassis backplane.
Figure 9. A PXI chassis incorporates the latest communication buses while routing to a variety of slot options to accommodate the requirements of a peripheral module.
In addition to the communication buses, the electrical specification also defines the timing and synchronization capabilities. It includes the definition of the PXI 10 MHz system clock, which is distributed to all peripheral modules in a system. This common reference clock can be used to synchronize multiple modules in a measurement or control system. In addition to clocking are PXI’s trigger capabilities such as a multidrop trigger bus and a matched trace length star trigger network. Eight PXI trigger lines form the PXI trigger bus, which is flexible and can be used in a variety of ways. For example, triggers can be used to synchronize the operation of several PXI peripheral modules.
Figure 10. The NI PXIe-1085 chassis PXI trigger bus connectivity diagram shows how to pass triggers to the PXI peripheral modules.
For applications that require higher performance, the specification defines the PXI star trigger network, which adds a higher performance synchronization feature set to the PXI system. The star trigger network implements a dedicated trigger line between the system timing slot (denoted by a diamond or square glyph surrounding the slot number, PXI and PXI Express, respectively) and the other peripheral slots. A timing and synchronization module—a star trigger controller—is installed in this slot to provide precise clocks and trigger signals to other peripheral modules. It can also override the PXI chassis’ onboard VCXO accuracy with its onboard (TCXO, OCXO), derived (DDS), or external (rubidium source) clock to define the chassis’ high-frequency system reference clock, 10 MHz and 100 MHz clocks.
Figure 11. The NI PXIe-1085 chassis uses this star connectivity diagram to ensure the propagation delay is matched among each slot.
Below you can see how the PXI trigger bus and PXI star trigger network are routed between the slots. To ensure compatibility between all of these features, the SYNC 100 was introduced to synchronize the 10 MHz and the 100 MHz clocks within a chassis.
Figure 12. Choose the most appropriate configuration to ensure the timing and synchronization capabilities fit your application needs.