Timing error describes how well you can measure or provide time. For example, if you measure a perfect 1 ms pulse and your measurement result is 1.003 ms, the 0.003 ms is your timing error in this measurement. When you report timing, timing error describes how well you provide the desired frequency. For instance, if you want to sample an analog voltage, you need a sample clock. Suppose you specify a 1 MHz sample clock while the actual sample clock frequency is 1.001 MHz. In this case, the 0.001 MHz frequency error represents the timing error.
Clock accuracy describes how well the actual frequency of the clock matches the specified frequency. Clock accuracy is described in parts per million (ppm). An accuracy of 5 ppm indicates that the mean frequency of the clock may be off by 5 Hz for every 1 MHz of its specified value. A 1 MHz clock with an accuracy of 5 ppm may have a frequency error of up to 5 Hz. A 2 MHz clock with the same accuracy may have a frequency error of up to 10 Hz.
Clock stability describes how well the clock frequency resists fluctuations. Factors that can cause the frequency to fluctuate include variations in temperature, time (aging), supply voltage, shock, vibration, and capacitive load that the clock must drive. Temperature is often the dominant factor that affects crystal oscillator stability.
The curve in Figure 10 represents the frequency of a 10 MHz clock over time. This clock is neither accurate nor stable. If you take the average value of the frequency, it is greater than 10 MHz. Furthermore, the value of the frequency fluctuates about a mean value over time.
Figure 10. Inaccurate, Unstable 10 MHz Clock
The curve in Figure 11 represents the frequency of a 10 MHz clock over time. If you take the average value of the frequency, it is very close to 10 MHz. Thus, this clock is accurate. However, the clock is not stable because the frequency fluctuates about its mean at approximately 10 MHz.
Figure 11. Unstable, Accurate 10 MHz Clock
The curve shown in Figure 12 represents the frequency of a 10 MHz clock over time. This clock is stable because its frequency does not fluctuate. However, because its frequency is greater than 10 MHz, it is not accurate.
Figure 12. Stable, Inaccurate 10 MHz Clock
The last curve, shown in Figure 13, represents the frequency of a 10 MHz clock over time. Its value is very close to 10 MHz and it shows very little or no fluctuations. Thus, this clock is accurate and stable.
Figure 13. Accurate, Stable 10 MHz Clock
Consider a system that has two clocks in two separate domains, as shown in Figure 14. If the clocks are started at exactly the same time, why do they drift apart from each other as time passes? Even identical clocks have small variances in frequency that, over time, add up to large differences and can cause the clocks to drift apart.
Figure 14. Separate Clock Domains
Clock drift occurs when two instruments are acquiring data at different sample rates. Even though two instruments are set for the “same” sample rate – for example, two digitizers acquiring at 100 MHz – the real oscillators on each instrument run at different rates and therefore clock drift occurs. Figure 15 shows an example of clock drift.
Figure 15. Clock Drift
One solution to remedy clock drift is to have a common clock domain for all modules in a system. If you use the clock of one device as the clock for all devices, then you can eliminate clock drift. Figure 16 shows an example of a common clock domain.
Figure 16. Common Clock Domains
Clock skew is a phenomenon in synchronous circuits in which the clock or trigger signals arrive at different slave devices at different times. Skew can be caused by many different things, such as wire-interconnect length, temperature variations, variation in intermediate devices, capacitive coupling, material imperfections, and differences in input capacitance on the clock inputs of devices using the clock. As the clock rate of a circuit increases, timing becomes more critical and less variation can be tolerated if the circuit is to function properly. Figure 17 shows an example of clock skew.
Figure 17. Clock Skew
One solution to clock skew is ensuring that all clock signal paths are the same length. The PXI chassis backplane has signal lines, called star trigger lines, which are equal in length. Clock signals distributed on these lines arrive at their destinations at the same time, eliminating skew. Figure 18 shows an example of the PXI backplane’s star trigger lines.
Figure 18. PXI Backplane with Star Trigger Lines
Clock jitter, the deviation from the ideal timing of an event, is typically measured from the zero-crossing of a reference event or signal. Jitter usually results from crosstalk, electromagnetic interference, simultaneous switching outputs, and other regularly occurring interference signals. Because jitter varies over time, the measurements and quantification of jitter can range from a visual estimate on a scope in seconds to a statistical-based measurement such as one based on the standard deviation over time. Figure 19 shows an example of clock jitter.
Figure 19. Clock Jitter