PCI Express is an evolution of the most popular computer peripheral bus in history, PCI. The industry consortium chartered to preserve and develop the PCI specification, the PCI Special Interest Group (PCI-SIG), developed PCI Express to address the bandwidth requirements of peripheral devices such as Gigabit Ethernet, modular storage devices, and high-end graphics while maintaining complete software compatibility with existing OSs and PCI-based applications. PCI Express is intended to replace the accelerated graphics port (AGP) that was developed to address PCI bandwidth limitations. PCI Express delivers 30 times the bandwidth of PCI and brings graphics back to the peripheral device bus, while increasing video bandwidth for the next generation of PCs.
Table 1. PCI Express Bandwidth Compared to PCI Bandwidth
Table 1 shows the scalable bandwidth that PCI Express delivers for different lane widths compared to PCI. For example, a x1 (“by one”) PCI Express slot delivers 250 MB/s in each direction while a x16 lane width supports 4 GB/s. A few applications that benefit from the increased bandwidth, economies of scale of PC technology, and software compatibility of PCI Express include high-speed data acquisition, vision systems, modular Ethernet storage, and high-channel-count digital I/O.
In January 2007, PCI-SIG announced the availability of the PCI Express 2.0 specification. It doubles the bus standard's bandwidth from 250 to 500 MB/s and includes improvements to the point-to-point data transfer protocol and its software architecture. The PCI Express 3.0 specification, scheduled to release in late 2009, doubles the standard bandwidth again to 1 GB/s.
|PCI Express Architecture
||Bandwidth Per Lane Direction
Table 2. PCI Express Specification Bandwidth per Lane