NI 9144 Expansion Chassis Under the Hood


EtherCAT RIO is a rugged expansion chassis for NI C Series modules. It uses an open, real-time Ethernet protocol to communicate with NI CompactRIO, PXI, and industrial controllers. This paper takes an in-depth look at the behind-the-scenes technologies that deliver the high-performance determinism of the EtherCAT RIO expansion chassis.


Expansion I/O With Real-Time Ethernet

The EtherCAT RIO expansion chassis uses a real-time Ethernet technology called EtherCAT (Ethernet Control Automation Technology) to communicate deterministically with a real-time master controller. This high-performance, industrial protocol extends the IEEE 802.3 Ethernet standard to transfer data with predictable timing and precise synchronization. Published as a part of IEC 61158, this open standard is commonly used in applications such as machine design and motion control.

To build your deterministic distributed I/O system, a master/slave architecture is used over standard Ethernet cabling. You can use any real-time CompactRIO, PXI, and NI industrial controller with two Ethernet ports as the master controller. Then daisy chain multiple EtherCAT RIO slave chassis from the master controller to expand your time-critical applications, all while maintaining hard determinism with minimal processor resources. However, note that you cannot connect the NI 9144 expansion chassis to a regular TCP/IP hub or a switch for implementing a star topology, because EtherCAT uses specially formatted EtherCAT telegrams to transfer data over the wire.

Figure 1. EtherCAT Master/Slave Architecture With CompactRIO Master Controller and NI 9144 Slave Chassis

Hardware Overview

The EtherCAT RIO expansion chassis consists of several hardware components that make deterministic distributed I/O possible. Each slave chassis comes with two Ethernet ports, which receive the EtherCAT packets. These packets are passed through the physical layer to the EtherCAT IP stack. The EtherCAT IP contains several fieldbus memory management units (FMMUs ) to correctly map the EtherCAT data addressed to a particular slave device. DMA transfers synchronous I/O data between the EtherCAT IP and the C Series I/O modules. The Xilinx field-programmable gate array (FPGA) acts as the C Series module interface, handling I/O reads and writes in a cyclic fashion based on instructions and timing from the EtherCAT IP. The Xilinx FPGA can also be programmed using the NI LabVIEW FPGA Module to embed high-speed logic on the EtherCAT RIO slave, such as I/O timing, triggering, and closed-loop control. The microcontroller manages any asynchronous messages between the master and slave, as well as various configuration tasks for the different hardware components.

Figure 2. EtherCAT RIO Hardware Block Diagram

Timing and Synchronization

The C Series module interface is part of a technology called the NI Scan Engine that was introduced with LabVIEW Real-Time 8.6 and CompactRIO. This component is responsible for synchronizing I/O data for the C Series modules, such that the I/O updates of the EtherCAT RIO seamlessly match the master’s cycle time.

The cycle time for the deterministic network consists of the total time for the master controller’s Program Scan and I/O Scan. The Program Scan includes the time for the LabVIEW program to process (both time-critical and normal tasks), any routine housekeeping and packet transfers with DMA and memory tables. The I/O Scan involves the time needed for the EtherCAT packet to pass through the entire slave network, downstream and back upstream.

Figure 3. Timing Diagram for Master and Slave Cycle Time

The cycle time for the EtherCAT RIO slave device consists of the total time for the Slave Update and I/O Scan. The Slave Update is the time the slave uses for DMA transfers, processing data, and updating its I/O. Since the I/O Scan is synchronized for the master and slave, the Slave Update runs at the same time as the master’s Program Scan. Therefore, the minimum cycle time is limited by either the Slave Update or Program Scan, depending on which takes longer.

Cycle Time   = Program Scan (memory transfer and data processing) + I/O Scan (data transfer)
= Slave Update (data updating and processing) + I/O Scan (data transfer)

The Program Scan time may increase with the number of slaves on the network, because the master controller has more data to process. However, the Slave Update time does not increase, because slaves update their I/O at the same time in parallel. Therefore, the more slaves that are on the network, the more likely the master Program Scan becomes the bottleneck. If your application involves high I/O channel count, consider using a high-performance processor for the master. For a detailed look at the effects of different controllers on the Program Scan rates, see the Benchmarks for the NI 9144 EtherCAT Slave Chassis white paper.

I/O Synchronization

The EtherCAT RIO expansion chassis has the advantage of not only module-to-module synchronization, but also slave-to-slave synchronization. The master controller does this by synchronizing all slave devices with the same time using distributed clocks. As soon as the I/O Scan is complete and the EtherCAT packet has been transferred, the EtherCAT IP fires the Sync0 signal to notify the slave that new data is available.

Figure 4. Timing Diagram for Slave Updates

The master controller also uses Sync0 to line up “Virtual Points,” exact points in time for all the slave chassis to update their I/O. Because the NI Scan Engine applies to single-point data, the Output Virtual Point is optimized to get the fastest update for output modules, and the Input Virtual Point is optimized to provide the most recent sample from input modules. With this paradigm in place, very low jitter occurs between the updates for any individual channel, which is ideal for control applications. For modules with multiplexed I/O, the inputs have a consistent amount of delay each cycle, such that the channel 0 read always has the same delta from the next channel 0 read. Additionally, simultaneous sampling modules have I/O channel updates at the exact same time for all identical modules used, and the phase offset is minimal even if using different modules. Assuming that each slave samples at the same two Virtual Points during the Slave Update, the outputs and inputs for all EtherCAT RIO slaves on the network have synchronized start times. 

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