Models that have a Primary Control Loop (PCL) set to parallel mode have a one-cycle delay between when a model executes and when the data it produces is available to the system.
As seen in the following illustration, the PCL will not wait for models to finish executing before it executes other steps.
In parallel mode, because the PCL does not wait for the models to finish executing before it executes other steps, models can continue executing even after the PCL starts its next iteration. During the next iteration, the model must finish executing before the PCL can read data from models. The following illustration shows how the VeriStand engine imposes this deadline in parallel mode.
To identify the model that was late, monitor the Time Step Duration execution channel for each model. This is useful when a system contains multiple models.
If you configure a model to run at a decimation of the PCL rate, the VeriStand engine enforces a deadline when the decimation specifies it to finish executing. For example, if the target rate for the PCL is 100 Hz and the decimation for a model is 2 (therefore, it runs at 50 Hz), the VeriStand Engine does not impose a deadline after the first 100 Hz PCL iteration because, according to the decimation, the model is not scheduled to finish executing.
However, after the second 100 Hz PCL iteration, when the model stops executing, the VeriStand Engine imposes a deadline. This happens on a per-model basis. A different model in the system with a decimation of 1 has a deadline imposed at every 100 Hz PCL iteration.