When modifying an FPGA VI, be aware of the guidelines and defaults.
Use the following guidelines
to avoid creating errors.
- Do not modify, remove, or rename block diagram objects in the gray areas of
the sample FPGA VI.
- Do not modify the read or write code except to change the number of packets
or to change the size of the array constant for the DMA read operation of
the DMA_WRITE FIFO.
- Ensure that the name of each control is unique within the VI.
- Do not use the following control/indicator names: Loop Rate (usec), Write to
RTSI, Use External Timing, Reset, Start, or Generate IRQ.
For more information on
creating FPGA VIs and bitfiles for an FPGA target, refer to the LabVIEW
Help by selecting in LabVIEW.
The process of creating a custom FPGA VI differs depending on
the hardware devices you are using. The default
defines the following FPGA I/O items for the PXI-7854R device:
- analog input channels 0–7
- analog output channels 0–7
- digital lines 0–39 on connectors 1 and 2
- digital lines 0–15 on connector 0
VeriStand uses direct memory access (DMA) FIFOs to transfer data between
the host computer and FPGA target. The DMA_READ FIFO
sends data read
from the FPGA inputs to the host computer. The DMA_WRITE FIFO
data from the host computer to the FPGA outputs. The data is stored in packets that
each can contain up to 64 bits. For example, you can pack four 16-bit signed (I16)
integer values into a single 64-bit packet. You can pack values of different data
types together in the same packet. If you add a channel to the FPGA VI, you also
must add the channel to a packet that is written to the FIFO.
Use the Join
Numbers function or Split Number function to