Add or remove FPGA I/O items depending on the device and the needs of the
By default, the sample FPGA VI only uses the first 40 lines on connectors 1 and 2. You
can add more FPGA I/O items to this project if you want to expose addition I/O lines on
For FPGA targets with
no analog inputs or outputs, you can remove the analog I/O items from the project and
the corresponding FPGA I/O Nodes from the FPGA VI.
Similarly, the default sample FPGA VI defines the digital lines on connector 0 as 8 PWM
inputs and 8 PWM outputs. You may need more or fewer PWM channels. You can add other
custom I/O not defined in the sample FPGA VI.
Optional: If the FPGA VI displays broken wires to FPGA I/O nodes, update the corresponding I/O
nodes with the correct pins available on the target.
Optional: If the number of packets in either the DMA_READ or DMA_WRITE FIFO is greater than 15,
update the FIFO size.
In Project Explorer window, right-click a FIFO I/O item and
In the FPGA FIFO Properties dialog box under General, change
the Number of Elements, and click