Configure counter output (CO) channel properties to generate digital pulses.
VeriStand generates digital pulses that
are defined by pairs of frequency and duty cycle values. Provide these values for
each counter output channel that generate pulses through two additional channels,
Frequency and Duty Cycle, that appear under the counter channels in System
The following illustration shows the parts of a
For more information on
generating pulses, refer to the NI-DAQmx Manual
To assign this measurement type
to channels on a non-X Series device, set Enable HWTSP to
False. If Enable HWTSP is
True, only X Series DAQ devices support this measurement
||Specifies the resting state of the output terminal:
- High—Terminal is at a high state at
rest. A pulse with a high idle state starts high, pulses to
low, and returns to high.
- Low—Terminal is at a low state at
rest. A pulse with a low idle state starts at the low value,
pulses high, and returns to low.
||Specifies the amount of time the output remains at the idle state
before generating the pulse. The idle state always replaces high
time or low time for the first pulse of a generation, depending on
the idle state.
- True—Generate pulses continuously
using hardware timing without a buffer. This timing type is
called hardware-timed single-point sample mode.
- False—Generates pulses continuously
without specifying timing. This timing type is called
implicit because the signal being measured
is itself the timing signal or the timing is implicit in the
rate of the generated pulse train.
Implicit timing is
appropriate when the measurement does not require sample
timing, such as with counters for buffered frequency
measurement, buffered period measurement, or pulse train
|HWTSP Clock Source
||If the Enable HWTSP property is True, this property specifies the
name of the source
terminal of the sample clock. Otherwise, this property is
ignored. You can use an internal counter timebase when performing
counter measurements or an external timebase.
A DAQ analog
channel with hardware-timed sample mode or an FPGA device must
be configured as the chassis master hardware synchronization
device on the Chassis Configuration page in System
Explorer. Otherwise, the clock source is not
available, and VeriStand returns an error during
|HWTSP Clock Rate
||If the Enable HWTSP property is True, this
property specifies the sampling rate in samples per channel per
second. Otherwise, this property is ignored. If you use an external
source for the sample clock, set this input to the maximum expected
rate of that
For device specific information about the default terminals used for counter
measurements and generations, refer to Connecting Counter Signals.
VeriStand limits how quickly you
can update the frequency and duty cycle values that define the pulses it generates.
At least one complete pulse must elapse with a set of frequency and duty cycle
values before you can change one of these values. If you update a value too quickly,
VeriStand reacts in one of the following ways:
- If the Enable HWTSP property is set to False,
VeriStand ignores the new value and continues using the latest value you
- If Enable HWTSP is set to True, VeriStand returns an