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Low Latency Primary Control Loop Timing in Models

Last Modified: March 27, 2020

Models in VeriStand that have a Primary Control Loop (PCL) set to low latency mode wait for the model to finish executing so other loops can access the data generated before executing again.

As seen in the following illustration, the PCL will let models transfer data before executing the next step.

Decimated Models

A model that is decimated returns values on every Nth iteration of the PCL, when N represents the decimation factor rather than every iteration as shown in the previous illustration. Additionally, passing data between decimated models causes an expected N tick delay where N represents the decimation factor.

Since decimated models run in parallel, they ignore the execution order you set in the system definition file. If you want to implement an execution order, add handshaking code to the decimated models.

Model Execution Deadlines

In low latency mode, the VeriStand engine does not enforce deadlines. The PCL waits for models to finish executing before moving to the next iteration. In other words, even though the late models delay the execution of VeriStand engine components, you can access data from models when needed. The Model Count and HP Count system channels increment when a model makes the PCL late.

To identify the model that made the PCL late, monitor the Time Step Duration execution channel for each model. This is useful when a system contains multiple models.

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