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Load Board Design

Last Modified: January 13, 2021

The VCSEL I-V Test Subsystem requires a connection to a load board to test packaged VCSEL DUTs. Use the following reference load board design and guidelines as a starting point when you create the load board design for your VCSEL I-V test application.

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Note  

You must design and supply the load board for your VCSEL I-V test application.

The reference load board design defines the essential components for the load board. You will need to modify and customize this design to satisfy the requirements of your specific VCSEL DUT. Refer to the following images to view a summary of the reference load board design.

Figure 1. Reference Load Board Design, Top Layer
  1. Sense ground plane
  2. Isolation barrier
  3. Pulse ground plane
  4. Primary BNC connector
  5. Secondary BNC connector
  6. Remote sense BNC connector
  7. Primary signal trace
  8. Secondary signal trace
  9. Remote sense signal trace
  10. Via
Figure 2. Reference Load Board Design, Bottom Layer
  1. Sense ground plane
  2. Isolation barrier
  3. Pulse input ground plane
  4. Primary BNC connector
  5. Secondary BNC connector
  6. Remote sense BNC connector
  7. Via

If you use the full impedance NI-4134 configuration for your VCSEL test application, you must remove the SECONDARY BNC connector from your load board design as well as the trace between the connector and the DUT. This path can cause signal distortion for the full impedance NI-4134 configuration.

Adhere to the following guidelines when designing a load board for the VCSEL I-V Test Subsystem:

  • Maintain 50 Ω impedance control for the PRIMARY trace, SECONDARY trace, and REMOTE SENSE trace.
  • Ensure an isolation barrier exists between the sense ground plane and the pulse ground plane to minimize AC current cross talk between planes. Only connect ground planes at the DUT pins on the load board.
  • Match the trace length from the PRIMARY receptacle and SECONDARY receptacle to the DUT exactly to ensure optimal measurement performance during DUT testing.
  • Place vias near signal traces to connect the top and bottom ground plane layers, and to maintain 50 Ω impedance.

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