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Table Of Contents

Hardware Overview

Version:
    Last Modified: July 30, 2021

    The Static Structural Test Reference Architecture is fundamentally a design pattern that you can use to instantiate a family of high-channel-count test systems, ranging from dozens to thousands of channels.

    Figure 1. Static Structural Test Reference Architecture Hardware Overview

    The Static Structural Test Reference Architecture comprises a combination of NI instrumentation and additional third-party hardware components grouped into a pattern of nodes, rings, and subsystems, further defined in the following sections. Refer to Designing Your System for more information about choosing the hardware components for your test system needs.

    Node

    A node is a single cDAQ-9189 TSN-enabled Ethernet CompactDAQ chassis configured with up to eight C series modules. The chassis serves as the foundation for all instrumentation in the test system and the modular design enables you to tailor the distribution and makeup of the channels in the system.

    The reference architecture is intended for test systems composed of mostly quarter bridge strain gauges; however, the design also supports thermocouple and voltage channel types. The reference architecture supports the following C Series modules:

    • NI-9235 C Series Strain/Bridge Input Module
    • NI-9236 C Series Strain/Bridge Input Module
    • NI-9213 C Series Temperature Input Module
    • NI-9215 C Series Voltage Input Module

    Ring

    A ring is a network of nodes arranged in a ring topology, as shown in the following figure. A ring topology introduces redundancy into the system design so that any single node or cable failure cannot cripple adjacent instrumentation.

    Figure 2. Ring Topology
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    Note  

    You can scale the design pattern for your test needs by expanding the number of nodes in each ring and number of rings in each test system.

    Network Aggregation Subsystem

    The network aggregation subsystem aggregates all ring communication down to a single port using the cRIO-9805 Ethernet Switch Expansion Modules for CompactRIO. The network aggregation subsystem can include as many Ethernet switches that are required to aggregate the ring count in your system. The Ethernet switches are arranged in a prescribed pattern depending on the amount of rings in your system design, as described in Aggregate Rings.

    Server Subsystem

    The server subsystem is a host PC that receives all the aggregated Ethernet communication across a dedicated network, then sends the test data across a shared network to operators and analysts interested in monitoring the tests.

    Figure 3. Detail View of Server Subsystem
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    Note  

    All node IP Addresses must be assigned and managed by a DHCP server.

    The server subsystem is responsible for test configuration and control and data logging. Refer to Software Overview for more information about the software components in the server subsystem.

    • Operator—Responsible for running and configuring the test on the host PC. The operator primarily interacts with FlexLogger to configure all instrumentation and test parameters and control the test system.
    • Analyst—Responsible for monitoring active test data and verifying the completeness and success of the test. The analyst primarily interacts with the Static Data Viewer web application on their analyst station to view relevant channels, configure local alarms, and add comments to the log file.

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