These specifications apply to the 8 MB, 32 MB, 256 MB, and 512 MB PXI-5422.
Specifications are valid under the following conditions unless otherwise noted:
Typical specifications are representative of an average unit and valid under the following conditions unless otherwise noted:
Number of channels |
1 |
Connector type |
SMB jack |
Path | Load | Amplitude (V pk-pk) | |
---|---|---|---|
Minimum | Maximum | ||
Direct | 50 Ω | 0.707 | 1.00 |
1 kΩ | 1.35 | 1.91 | |
Open | 1.41 | 2.00 | |
Low-gain amplifier | 50 Ω | 0.00564 | 2.00 |
1 kΩ | 0.0107 | 3.81 | |
Open | 0.0113 | 4.00 | |
High-gain amplifier | 50 Ω | 0.0338 | 12.0 |
1 kΩ | 0.0644 | 22.9 | |
Open | 0.0676 | 24.0 |
Amplitude resolution |
<0.06% (0.004 dB) of Amplitude Range |
Offset range[4] |
Span of ±50% of Amplitude Range with increments <0.0028% of Amplitude Range |
Path | Load | Maximum Output Voltage (V) |
---|---|---|
Direct | 50 Ω | ±0.500 |
1 kΩ | ±0.953 | |
Open | ±1.000 | |
Low-gain amplifier | 50 Ω | ±1.000 |
1 kΩ | ±1.905 | |
Open | ±2.000 | |
High-gain amplifier | 50 Ω | ±6.000 |
1 kΩ | ±11.43 | |
Open | ±12.00 |
Path | DC Accuracy | |
---|---|---|
±10 °C of Self-Calibration Temperature | 0 °C to 55 °C | |
Low-gain amplifier | ±0.2% of Amplitude Range ± 0.05% of Offset ± 500 µV | ±0.4% of Amplitude Range ± 0.05% of Offset ± 1 mV |
High-gain amplifier | ||
Path | Gain Accuracy | |
±10 °C of Self-Calibration Temperature | 0 °C to 55 °C | |
Direct | ±0.2% Amplitude Range | ±0.4% Amplitude Range |
Analog filter[12] |
Software-selectable: 7-pole elliptical filter for image suppression |
Path | Rise/Fall Time (ns), Typical | Aberration (%), Typical |
---|---|---|
Direct | 1.0 | 16 |
Low-gain amplifier | 2.1 | 6 |
High-gain amplifier | 4.8 | 8 |
Path | Frequency (MHz) | |||
---|---|---|---|---|
Sine | Square[15] | Ramp[15] | Triangle[15] | |
Direct | 80 | Not recommended | ||
Low-gain amplifier | 50 | 10 | ||
High-gain amplifier | 43 | 25 |
Frequency | SFDR with Harmonics (dB), Typical | ||
---|---|---|---|
Direct Path | Low-Gain Amplifier Path | High-Gain Amplifier Path | |
1 MHz | 70 | 65 | 66 |
5 MHz | 58 | ||
10 MHz | 52 | ||
20 MHz | 63 | 64 | 49 |
30 MHz | 57 | 60 | 43 |
40 MHz | 48 | 53 | 39 |
50 MHz | — | ||
60 MHz | 47 | 52 | |
70 MHz | |||
80 MHz | 41 |
Frequency | SFDR without Harmonics (dB), Typical | ||
---|---|---|---|
Direct Path | Low-Gain Amplifier Path | High-Gain Amplifier Path | |
1 MHz | 84 | 79 | 76 |
5 MHz | |||
10 MHz | 79 | ||
20 MHz | |||
30 MHz | 72 | 70 | 67 |
40 MHz | 47 | 57 | 54 |
50 MHz | 52 | — | |
60 MHz | 46 | 51 | |
70 MHz | |||
80 MHz | 40 |
Amplitude Range | Average Noise Density, Typical | |||
---|---|---|---|---|
dBm/Hz | dBFS/Hz | |||
1.00 V pk-pk | 4.0 dBm | 19.9 | -141 | -145 |
Amplitude Range | Average Noise Density, Typical | |||
---|---|---|---|---|
dBm/Hz | dBFS/Hz | |||
0.06 V pk-pk | -20.5 dBm | 1.3 | -148 | -144 |
0.10 V pk-pk | -16.0 dBm | 2.2 | ||
0.40 V pk-pk | -4.0 dBm | 8.9 | ||
1.00 V pk-pk | 4.0 dBm | 22.3 | -140 | |
2.00 V pk-pk | 10.0 dBm | 44.6 | -134 |
Amplitude Range | Average Noise Density, Typical | |||
---|---|---|---|---|
dBm/Hz | dBFS/Hz | |||
4.00 V pk-pk | 16.0 dBm | 93.8 | -128 | -144 |
12.00 V pk-pk | 25.6 dBm | 281.5 | -118 |
|
Sample Clock Source | Sample Rate Range (MS/s) |
---|---|
Divide-by-N | 5 to 200 |
High-Resolution | 5 to 100 |
>100 to 200 | |
CLK IN | 5 to 200 |
DDC CLK IN | |
PXI Star Trigger | 5 to 105 |
PXI_Trig <0..7> | 5 to 20 |
Sample Clock Source | Sample Rate Resolution |
---|---|
Divide-by-N | Configurable to (200 MS/s)/N (1 ≤ N ≤ 40) |
High-Resolution | 1.06 µHz |
4.24 µHz | |
CLK IN | Resolution determined by external clock source. External Sample Clock duty cycle tolerance 40% to 60%. |
DDC CLK IN | |
PXI Star Trigger | |
PXI_Trig <0..7> |
Sample Clock Source | Delay Adjustment Range |
---|---|
Divide-by-N | ±1 Sample Clock period |
High-Resolution | |
CLK IN | 0 ns to 7.6 ns |
DDC CLK IN | |
PXI Star Trigger | |
PXI_Trig <0..7> |
Sample Clock Source | System Phase Noise Density Offset (dBc/Hz), Typical | ||
---|---|---|---|
100 Hz | 1 kHz | 10 kHz | |
Divide-by-N | -110 | -122 | -138 |
High-Resolution[21] 100 MS/s | -109 | -120 | -120 |
High-Resolution[21] 200 MS/s | -108 | -122 | |
CLK IN | -116 | -130 | -143 |
PXI Star Trigger[22] | -111 | -128 | -136 |
Sample Clock Source | System Output Jitter (ps rms), Typical |
---|---|
Divide-by-N | 1.5 |
High-Resolution[21] 100 MS/s | 4.0 |
High-Resolution[21] 200 MS/s | 4.2 |
CLK IN | 1.1 |
PXI Star Trigger[22] | 2.1 |
|
Destinations[24] |
PFI <0..1> (SMB front panel connectors) DDC CLK OUT (DIGITAL DATA & CONTROL front panel connector) PXI_Trig <0..6> (backplane connector) |
||||||||
|
|||||||||
|
|||||||||
|
Source |
Internal Sample Clocks can either be locked to a Reference Clock using a phase-locked loop or derived from the onboard VCXO frequency reference. |
Frequency accuracy |
±25 ppm |
Sources[25] |
PXI_CLK10 (backplane connector) CLK IN (SMB front panel connector) |
Frequency accuracy |
When using the PLL, the frequency accuracy of the PXI-5422 is solely dependent on the frequency accuracy of the PLL Reference Clock source. |
Lock time |
≤200 ms, typical |
Frequency range[26] |
5 MHz to 20 MHz in increments of 1 MHz[27] |
Duty cycle range |
40% to 60% |
Destinations |
PFI <0..1> (SMB front panel connectors) PXI_Trig <0..6> (backplane connector) |
Connector type |
SMB jack |
||||||
Direction |
Input |
||||||
Destinations |
Sample Clock PLL Reference Clock |
||||||
|
|||||||
|
|||||||
Maximum input overload |
±10 V |
||||||
Input impedance |
50 Ω |
||||||
Input coupling |
AC |
Connector type |
SMB jack (x2) |
||||||||||||||||||||||||||
Direction |
Bidirectional |
||||||||||||||||||||||||||
Frequency range |
DC to 200 MHz |
||||||||||||||||||||||||||
|
|||||||||||||||||||||||||||
|
Connector type |
68-pin VHDCI female receptacle |
Number of data output signals |
16 |
Control signals |
DDC CLK OUT (clock output) DDC CLK IN (clock input) PFI 2 (input) PFI 3 (input) PFI 4 (output) PFI 5 (output) |
Ground |
23 pins |
|
|||||||||||||
Output skew[31] |
1 ns, typical 2 ns, maximum |
||||||||||||
Output enable/disable |
Controlled through the software on all data output signals and control signals collectively. When disabled, the output signals go to a high-impedance state. |
||||||||||||
Maximum output overload |
-0.3 V to +3.9 V |
Signal type |
Low-voltage differential signal (LVDS) |
Input differential impedance |
100 Ω |
Maximum output overload |
-0.3 V to +3.9 V |
Differential input voltage |
0.1 V, minimum 0.5 V, maximum |
Input common mode voltage |
0.2 V, minimum 2.2 V, maximum |
Clocking format |
Data outputs and markers change on the falling edge of DDC CLK OUT. |
Frequency range |
Refer to the Sample Clock section for more information. |
Duty cycle |
35% to 65% |
Jitter |
60 ps rms, typical |
Sources |
PFI <0..1> (SMB front panel connectors) PFI <2..3> (DIGITAL DATA & CONTROL front panel connector) PXI_Trig <0..7> (backplane connector) PXI Star Trigger (backplane connector) Software (use node or function call) Immediate (does not wait for a trigger)[32] |
Trigger modes |
Single Continuous Stepped Burst |
Edge detection |
Rising |
Minimum pulse width |
25 ns |
Delay from Start Trigger to CH 0 analog output |
65 Sample Clock periods + 110 ns |
Delay from Start Trigger to digital data output |
41 Sample Clock periods + 110 ns |
Destinations |
A signal used as a trigger can be routed out to any destination listed in the Destinations specification of the Markers section. |
Exported trigger delay |
65 ns, typical |
Exported trigger pulse width |
>150 ns |
Destinations |
PFI <0..1> (SMB front panel connectors) PFI <4..5> (DIGITAL DATA & CONTROL front panel connector) PXI_Trig <0..6> (backpane connector) |
||||||
Quantity |
One marker per segment |
||||||
Quantum |
Marker position must be placed at an integer multiple of four samples. |
||||||
Width |
>150 ns |
||||||
|
|||||||
|
|||||||
Jitter |
40 ps rms, typical |
Memory usage |
The PXI-5422 uses the Synchronization and Memory Core (SMC) technology in which waveforms and instructions share onboard memory. Parameters—such as number of segments in sequence list, maximum number of waveforms in memory, and number of samples available for waveform storage—are flexible and user-defined. |
||||||||||
|
|||||||||||
Output modes |
Arbitrary waveform[33] Arbitrary sequence[34] |
Trigger Mode | Minimum Waveform Size (Samples) | ||
---|---|---|---|
Arbitrary Waveform Mode | Arbitrary Sequence Mode[35] | ||
At >50 MS/s | At ≤50 MS/s | ||
Single | 16 | ||
Continuous | 32 | 192 | 96 |
Stepped | |||
Burst |
Loop count |
1 to 16,777,215 Burst trigger: Unlimited |
Quantum |
Waveform size must be an integer multiple of four samples. |
Onboard Memory | Maximum Waveform Memory (Samples) | |
---|---|---|
Arbitrary Waveform Mode | Arbitrary Sequence Mode[37] | |
8 MB standard | 4,194,176 | 4,194,048 |
32 MB option | 16,777,088 | 16,776,960 |
256 MB option | 134,217,600 | 134,217,472 |
512 MB option | 268,435,328 | 268,435,200 |
Onboard Memory | Maximum Waveforms |
---|---|
8 MB standard | 65,000 |
Burst trigger: 8,000 | |
32 MB option | 262,000 |
Burst trigger: 32,000 | |
256 MB option | 2,097,000 |
Burst trigger: 262,000 | |
512 MB option | 4,194,000 |
Burst trigger: 524,000 |
Onboard Memory | Maximum Segments in a Sequence |
---|---|
8 MB standard | 104,000 |
Burst trigger: 65,000 | |
32 MB option | 418,000 |
Burst trigger: 262,000 | |
256 MB option | 3,354,000 |
Burst trigger: 2,090,000 | |
512 MB option | 6,708,000 |
Burst trigger: 4,180,000 |
Self-calibration |
An onboard, 24-bit ADC and precision voltage reference are used to calibrate the DC gain and offset. The self-calibration is initiated by the user through the software and takes approximately 90 seconds to complete. |
External calibration |
External calibration calibrates the VCXO, voltage reference, DC gain, and offset. Appropriate constants are stored in nonvolatile memory. |
Calibration interval |
Specifications valid within two years of external calibration. |
Warm-up time |
15 minutes |
Power | ||
---|---|---|
Typical Operation[39] | Overload Operation[40] | |
+3.3 V DC | 2 A | |
+5 V DC | Refer to Figure 13. | 2.7 A |
+12 V DC | 0.46 A | |
-12 V DC | 0.01 A | |
Total | 12.2 W + 5 V × 5 V current | 25.7 W |
Dimensions |
3U, one-slot, PXI/cPCI module[41] 21.6 cm × 2.0 cm × 13.0 cm (8.5 in. × 0.8 in. × 5.1 in.) |
Weight |
352 g (12.4 oz) |
Maximum altitude |
2,000 m (at 25 °C ambient temperature) |
Pollution Degree |
2 |
|
|||||||
|
This product is designed to meet the requirements of the following electrical equipment safety standards for measurement, control, and laboratory use:
For UL and other safety certifications, refer to the product label or the Product Certifications and Declarations section.
For EMC declarations and certifications, refer to the Online Product Certification section.
This product meets the essential requirements of applicable European Directives, as follows:
Refer to the product Declaration of Conformity (DoC) for additional regulatory compliance information. To obtain product certifications and the DoC for NI products, visit ni.com/certification, search by model number or product line, and click the appropriate link in the Certification column.
NI is committed to designing and manufacturing products in an environmentally responsible manner. NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers.
For additional environmental information, refer to the Minimize Our Environmental Impact web page at ni.com/environment. This page contains the environmental regulations and directives with which NI complies, as well as other environmental information not included in this document.
At the end of the product life cycle, all NI products must be disposed of according to local laws and regulations. For more information about how to recycle NI products in your region, visit ni.com/environment/weee.