Refer to the following figure and tables for information about the PXI-5421 front panel connectors and LEDs:
Table 1.
PXI-5421 Signal Descriptions
Signal |
Connector Type |
Access |
Description |
CH 0 |
SMB |
Output |
Generates waveforms from an analog output terminal. |
CLK IN |
Input |
Accepts an external PLL Reference Clock and can phase-lock the internal Sample Timebase Clock to the external Reference Clock. The signal on this connector can also be used as a Sample Clock source. |
PFI 0 |
Input/Output |
Accepts a trigger from an external source and can start or step through waveform generation or route signals from several clock, event, and trigger sources. |
PFI 1 |
DIGITAL DATA & CONTROL (DDC) |
68-pin male
VHDCI |
Routes the 16-bit digital pattern outputs, digital pattern clock output, trigger outputs, trigger inputs, and a clock input. |
Note
The DDC connector is not available on the PXI-5421 8 MB memory option.
Table 2.
PXI-5421 ACCESS LED Indicators
The ACCESS LED indicates basic hardware status.
LED Color |
Indication |
No color (off) |
The PXI-5421 is not yet functional, or the PXI-5421 has detected a problem with a power rail. |
Amber |
The PXI-5421 is being accessed. |
Green |
The PXI-5421 is ready to be programmed by NI-FGEN. |
Table 3.
PXI-5421 ACTIVE LED Indicators
The ACTIVE LED indicates the
PXI-5421 hardware state.
LED Color |
Indication |
No color (off) |
The PXI-5421 is not generating. |
Amber |
The PXI-5421 is armed and waiting for a trigger. |
Green |
The PXI-5421 has received a trigger and is generating a waveform. |
Red |
The PXI-5421 has detected an error. NI-FGEN must access the PXI-5421 to determine the cause of the error. The LED remains red until the error condition is removed. Example errors include the following:
-
Phase-locked loop (PLL) unlocked: The PXI-5421 has detected an unlocked condition on a previously locked PLL. A PLL that is unlocked while in reset does not show an error.
-
The PXI-5421 has powered down because the internal temperature exceeded the maximum limit. The over-temperature condition must be corrected and the hardware reset. To reset the hardware, call niFgen Reset Device or niFgen_ResetDevice, or perform a device reset in MAX.[1]
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