This section lists the system specifications for PXIe-6674T modules. These specifications are typical at 25 °C, unless otherwise stated.
x denotes all letter revisions of the assembly. Ensure the specifications of interest match the revision that is printed on the label.
Warranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty.
The following characteristic specifications describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.
Input coupling |
AC |
Input impedance |
50 Ω, nominal |
Setting | Attenuation Setting On | Attenuation Setting Off |
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Attenuation Setting | On (default) | Off |
Attenuation Behavior | 5:1 | 1:1 |
Minimum Input Swing with 50% Duty Cycle[1] | 750 mVpp | 150 mVpp |
Maximum Input Swing with 50% Duty Cycle[2] | 5.0 Vpp | 1.2 Vpp |
Absolute Maximum Input Powered On[3] | 5.6 Vpp | 2.8 Vpp |
Absolute Maximum Input Powered Off [4] | 1.5 Vpp |
Minimum Frequency |
1 MHz[5] |
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Nominal Frequency |
10 MHz |
Accuracy within 1 year of calibration adjustment within 0 °C to 55 °C operating temperature range [6] |
± 80 ppb |
Long-term stability |
±50 ppb/year |
Stability vs temperature |
<10 ppb peak-to-peak within 0 °C to 55 °C operating temperature range |
Tuning Range |
±1.5 ppm minimum, ±2 ppm typical, ±4 ppm maximum |
Tuning DAC Resolution |
16 bits, 0.0625 ppb per step typical |
Recommended calibration interval |
1 year |
Offset | Phase Noise |
---|---|
1 Hz | -80 dBc/Hz |
10 Hz | -120 dBc/Hz |
100 Hz | -140 dBc/Hz |
1 kHz | -145 dBc/Hz |
10 kHz | -150 dBc/Hz |
The following figure shows the phase noise on a representative module. OCXO is routed to the ClkOut SMA, measured in a PXIe-1082 chassis with low fan speed[7]. The integrated jitter from 10 Hz to 1 MHz is 507 fs rms
.The following figure shows the phase noise on a representative module of PXI_CLK10 when OCXO is routed to PXI_CLK10_IN,[8] measured in a PXIe-1082 chassis with low fan speed:
Reference Frequency Range (from ClkIn) |
1 MHz to 100 MHz, in increments of 1 MHz |
Recommended ClkIn Frequency[9] |
10 MHz |
Reference Frequency Required Accuracy |
± 1.5 ppm |
Reference Frequency Duty Cycle |
40% to 60% |
PLL Loop Bandwidth |
100 Hz |
Maximum PXI_CLK10 Phase Offset |
+/- 1 ns |
The following figure shows the phase noise on a representative module of PXI_CLK10 when CLKIN is routed to PXI_CLK10_IN with and without the 10 MHz PLL, measured in a PXIe-1082 chassis with low fan speed.[10]
Low Speed ClkOut | High Speed ClkOut | |
---|---|---|
Coupling | AC Coupled | AC Coupled |
Expected Termination | 50 Ω or high impedance | 50 Ω |
Frequency Range | 1 MHz to 50 MHz[11] | 1 MHz to 1 GHz[12] |
Typical Amplitude | 2.57 Vpp into 50 Ω, 5 Vpp into high Z | 800 mVpp |
Rising/Falling Edge (20%, 80%) | 270 ps, typical | 180 ps, typical |
Duty Cycle of output with Clock Generation as source | 45% to 55% | 45% to 55% |
Available Sources | PXI_CLK10, 10 MHz OCXO, Clock Generation up to 50 MHz | Clock Generation, PXIe-DStarA Network[13] |
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The following figure shows the typical Low Speed ClkOut Amplitude performance, with a sample size of 19 modules.
The following figure shows the typical High Speed ClkOut Amplitude performance, with a sample size of 19 modules.
Reference Frequency Source[14] |
PXIe_Clk100 |
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Base Frequency Resolution (150 MHz to 300 MHz) |
2.84217 μHz[15] |
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Maximum Generated Frequency |
1 GHz[17] |
The phase noise performance of the clock generation circuitry varies depending on what elements are used to generate the requested frequency. To generate frequencies above 300 MHz, a PLL is used to multiply the DDS frequency up which results in increased phase noise versus when the DDS is used directly (all frequencies below 300 MHz).
The following figure shows the phase noise of various frequencies coming from the multiplying PLL.
At 50 MHz, NI-Sync software will automatically switch between the high speed and low speed ClkOut drivers[18]. The phase noise performance of these two drivers differs, as shown in the following figure:
PXIe-DStarA Maximum Frequency |
1 GHz[19] |
Minimum | Typical | Maximum | |
---|---|---|---|
Voltage High Output | 2.155 V | 2.280 V | 2.405 V |
Voltage Low Output | 1.355 V | 1.530 V | 1.700 V |
Rise Time/Fall Time 20%, 80% | 125 ps | 180 ps | 275 ps |
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Termination Setting | High Impedance | 50 Ω |
Input Impedance | 10kΩ, ± 20% | 50 Ω, ± 5% |
Input Coupling | DC | DC |
Hysteresis | 50 mV typical | 58 mV typical (Revision C and D)[20], 53 mV typical (Revision E and later)[20] |
Adjustable Threshold Range | 15 mV to 3.795 V | 16.8 mV to 4.25 V (Revision C and D)[20], 15.975 mV to 4.04 V (Revision E and later)[20] |
Adjustable Threshold Resolution | 15 mV | 16.8 mV (Revision C and D)[20], 15.975 mV (Revision E and later)[20] |
Adjustable Threshold Error[21] | ± 5 mV | ± 5 mV |
Default Threshold Setting | 1.005 V | 1.008 V (Revision C and D)[20], 1.006 V (Revision E and later)[20] |
Minimum Input Voltage Swing[22] | 400 mVpp | 450 mVpp |
Frequency Range[23] | DC to 150 MHz | DC to 150 MHz |
Recommended Maximum Input Voltage Range | 0.0 V to 5.0 V | 0.0 V to 5.0 V |
Maximum Input Voltage Range | –0.5 V to 5.5 V | –0.5V to 5.5 V |
PFI Open Circuit Voltage[24] | 0.45 V, typical | N/A |
Output Impedance | 50 Ω, nominal |
Output Coupling | DC |
Output Voltage Range into 50 Ω load | 0 V to 1.63 V, typical |
Output Voltage Range into open load | 0 V to 3.22 V, typical |
Output Rising/Falling Edge into 50 Ω load | 450 ps to 500 ps, 20%–80%, typical |
Maximum Output Frequency[25] | DC to 150 MHz |
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The following figure shows the representative LVDS output operating at 100 MHz. 1 unit interval in this figure equals 5 ns.
The following figure shows the representative LVDS output operating at 1 GHz. 1 unit interval in the figure equals 500 ps.
The PXIe-DStarB signals are LVDS signals that allow the PXIe-6674T to route high speed trigger signals to any other PXIe slot in a chassis. Each PXI Express slot in a chassis has its own PXIe-DStarB connection with the System Timing Slot.
By default, these are driven logic low until configured by software.
Maximum operating frequency |
200 MHz |
The PXIe-DStarC signals are LVDS signals that come from other PXI Express slots in a chassis. Each PXI Express slot in a chassis has a PXIe-DStarC connection with the System Timing Slot. These allow other modules in a PXIe-Chassis to share a trigger or clock signal with the PXIe-6674T. The PXIe-6674T can connect a signal received through PXIe-DStarC to the PXIe-DStarA network (when sharing a clock signal) or treat the PXIe-DStarC as a trigger source.
Maximum operating frequency when used with the PXIe-DStarA network |
1 GHz |
Maximum operating frequency when used for triggering |
200 MHz |
Trigger Source | Trigger Destination | Typical Delay[32] | Typical Skew[33] |
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Single Ended PFI | Single Ended PFI | 23.4 ns | < .5 ns |
Single Ended PFI | LVDS PFI | 22.4 ns | < .5 ns |
Single Ended PFI | PXI-Trigger | 38.7 ns | < 1.5 ns |
Single Ended PFI | PXI-Star | 26.8 ns | < .75 ns |
Single Ended PFI | PXIe-DStarB | 23.2 ns | < .5 ns |
LVDS PFI | Single Ended PFI | 13.7 ns | < .5 ns |
LVDS PFI | LVDS PFI | 11.8 ns | < .5 ns |
LVDS PFI | PXI-Trigger | 28.9 ns | < 1.5 ns |
LVDS PFI | PXI-Star | 17.5 ns | < .75 ns |
LVDS PFI | PXIe-DStarB | 13.8 ns | < .5 ns |
PXI-Trigger | Single Ended PFI | 17.8 ns | < .5 ns |
PXI-Trigger | LVDS PFI | 16.6 ns | < .5 ns |
PXI-Trigger | PXI-Trigger | 33.8 ns | < 1.5 ns |
PXI-Trigger | PXI-Star | 21.0 ns | < .75 ns |
PXI-Trigger | PXIe-DStarB | 15.9 ns | < .5 ns |
PXI-Star | Single Ended PFI | 17.0 ns | < .5 ns |
PXI-Star | LVDS PFI | 15.6 ns | < .5 ns |
PXI-Star | PXI-Trigger | 26.2 ns | < 1.5 ns |
PXI-Star | PXI-Star | 20.2 ns | < .75 ns |
PXI-Star | PXIe-DStarB | 16.0 ns | < .5 ns |
PXIe-DStarC | Single Ended PFI | 13.6 ns | < .5 ns |
PXIe-DStarC | LVDS PFI | 7.2 ns | < .5 ns |
PXIe-DStarC | PXI-Trigger | 28.1 ns | < 1.5 ns |
PXIe-DStarC | PXI-Star | 16.8 ns | < .75 ns |
PXIe-DStarC | PXIe-DStarB | 13.0 ns | < .5 ns |
Trigger Destination | Clock to Out Time[34] |
---|---|
Single Ended PFI | 11.2 ns Typical, 19.9 ns Max |
LVDS PFI | 9.8 ns Typical, 14.8 ns Max |
PXI-Trigger | 28.2 ns Typical, 30.2 ns Max |
PXI-Star | 14.8 ns Typical, 24.5 ns Max |
PXIe-DStarB | 9.4 ns Typical, 14.0 ns Max |
Trigger Source | Trigger Destination | Setup Time[35] | Hold Time[36] |
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Single Ended PFI | Single Ended PFI | 11.2 ns Typical, 13.2 ns Max | -8.2 ns Typical, 1.1 ns Max |
Single Ended PFI | LVDS PFI | 11.2 ns Typical, 13.5 ns Max | -8.5 ns Typical, 0.8 ns Max |
Single Ended PFI | PXI-Trigger | 11.3 ns Typical, 14.2 ns Max | -7.5 ns Typical, 1.3 ns Max |
Single Ended PFI | PXI-Star | 11.2 ns Typical, 13.1 ns Max | -6.9 ns Typical, 2.0 ns Max |
Single Ended PFI | PXIe-DStarB | 13.2 ns Typical, 15.4 ns Max | -9.8 ns Typical, -0.4 ns Max |
LVDS PFI | Single Ended PFI | 0.6 ns Typical, 4.0 ns Max | 0.4 ns Typical, 3.9 ns Max |
LVDS PFI | LVDS PFI | -0.3 ns Typical, 4.3 ns Max | 1.2 ns Typical, 3.5 ns Max |
LVDS PFI | PXI-Trigger | -0.2 ns Typical, 3.6 ns Max | 1.1 ns Typical, 5.0 ns Max |
LVDS PFI | PXI-Star | -0.1 ns Typical, 3.7 ns Max | 1.4 ns Typical, 5.0 ns Max |
LVDS PFI | PXIe-DStarB | 2.1 ns Typical, 5.7 ns Max | -0.5 ns Typical, 2.6 ns Max |
PXI-Trigger | Single Ended PFI | 11 ns Typical, 17.5 ns Max | -9.5 ns Typical, -4.8 ns Max |
PXI-Trigger | LVDS PFI | 10.9 ns Typical, 18.1 ns Max | -9.8 ns Typical, -5.4 ns Max |
PXI-Trigger | PXI-Trigger | 10.1 ns Typical, 17.0 ns Max | -7.8 ns Typical, -3.6 ns Max |
PXI-Trigger | PXI-Star | 9.7 ns Typical, 16.2 ns Max | --7.4 ns Typical, -3.1 ns Max |
PXI-Trigger | PXIe-DStarB | 10.7 ns Typical, 17.8 ns Max | -9.0 ns Typical, -5.1 ns Max |
PXI-Star | Single Ended PFI | 3.9 ns Typical, 10.9 ns Max | -2.5 ns Typical, -0.5 ns Max |
PXI-Star | LVDS PFI | 3.9 ns Typical, 11.1 ns Max | -3.1 ns Typical, -0.8 ns Max |
PXI-Star | PXI-Trigger | 2.7 ns Typical, 9.9 ns Max | -0.9 ns Typical, 0.9 ns Max |
PXI-Star | PXI-Star | 2.0 ns Typical, 9.6 ns Max | -0.1 ns Typical, 1.1 ns Max |
PXI-Star | PXIe-DStarB | 4.3 ns Typical, 11.7 ns Max | -2.4 ns Typical, -1.1 ns Max |
PXIe-DStarC | Single Ended PFI | 0.5 ns Typical, 3.9 ns Max | 0.4 ns Typical, 3.7 ns Max |
PXIe-DStarC | LVDS PFI | -0.3 ns Typical, 4.4 ns Max | 0.5 ns Typical, 3.1 ns Max |
PXIe-DStarC | PXI-Trigger | -1.1 ns Typical, 2.8 ns Max | 1.9 ns Typical, 5.2 ns Max |
PXIe-DStarC | PXI-Star | -0.5 ns Typical, 3.2 ns Max | 3.1 ns Typical, 4.9 ns Max |
PXIe-DStarC | PXIe-DStarB | 1.3 ns Typical, 5.6 ns Max | 0.2 ns Typical, 2.4 ns Max |
Two independent synchronization clock zones:
Synchronization Clock Sources |
PXI_Clk10, PXIe_Clk100, Clock In, OCXO, and Clock Generation |
Two division ratios can be specified in powers of 2 from 2 to 512. These ratios are used in all synchronization clock zones to divide down the selected full speed synchronization clock.
Chassis requirement |
One 3U PXI Express slot (system timing slot) |
Front panel connectors |
Eight SMA female, 50 Ω |
Front panel indicators |
Two tricolor LEDs (green, red, and amber) |
Weight |
349 g (12.3 oz) |
Dimensions (not including connectors) |
16 cm × 10 cm (6.3 in. × 3.9 in.) |
Maximum altitude |
2,000 m (800 mbar) (at 25 °C ambient temperature) |
Pollution Degree |
2 |
Indoor use only.
Ambient temperature range |
0 to 55 °C (Tested in accordance with IEC-60068-2-1 and IEC-60068-2-2. Meets MIL-PRF-28800F Class 3 low temperature limit and MIL-PRF-28800F Class 2 high temperature limit.) |
Relative humidity range |
10% to 90%, noncondensing (Tested in accordance with IEC-60068-2-56.) |
Operating Shock |
30 g peak, half-sine, 11 ms pulse (Tested in accordance with IEC-60068-2-27. Meets MIL-PRF-28800F Class 2 limits.) |
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This product is designed to meet the requirements of the following electrical equipment safety standards for measurement, control, and laboratory use:
For UL and other safety certifications, refer to the product label or the Online Product Certification section.
This product meets the requirements of the following EMC standards for electrical equipment for measurement, control, and laboratory use; for radio equipment; and for telecommunication terminal equipment:
For EMC declarations and certifications, and additional information, refer to the Online Product Certification section.
This product meets the essential requirements of applicable European Directives, as follows:
Refer to the product Declaration of Conformity (DoC) for additional regulatory compliance information. To obtain product certifications and the DoC for this product, visit ni.com/certification, search by model number or product line, and click the appropriate link in the Certification column.
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For additional environmental information, refer to the Minimize Our Environmental Impact web page at ni.com/environment. This page contains the environmental regulations and directives with which NI complies, as well as other environmental information not included in this document.
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