Warranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty. Warranted specifications account for measurement uncertainties, temperature drift, and aging. Warranted specifications are ensured by design or verified during production and calibration.
Characteristics describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.
Specifications are valid under the following conditions unless otherwise noted.
Warranted specifications are valid under the following conditions unless otherwise noted.
Typical specifications are valid under the following conditions unless otherwise noted.
Number of channels |
Two (simultaneously sampled) |
Input type |
Referenced single-ended |
Connectors |
BNC, ground referenced |
Input impedance |
50 Ω ±1.25%, typical 1 MΩ ±0.5%, typical |
Input capacitance (1 MΩ) |
20.2 pF ±2.5 pF, typical |
Input coupling |
AC DC |
50 Ω FS input range (Vpk-pk) |
0.25 V 0.5 V 1 V 2.5 V 5 V |
Input Range (Vpk-pk) | Vertical Offset Range[1] (V) |
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0.25 V | ±5 |
0.5 V | ±5 |
1 V | ±5 |
2.5 V | ±10 or ±248.75 |
5 V | ±10 or ±247.5 |
10 V | ±10 or ±245 |
25 V | ±50 or ±237.5 |
50 V | ±50 or ±225 |
100 V | ±50 or ±200 |
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Resolution |
14 bits |
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DC drift[5] |
±[(0.015% × |Reading - Vertical Offset|) + (0.001% × |Vertical Offset|) + (0.009% of FS)] per °C, nominal |
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AC amplitude accuracy[3] |
±0.2 dB at 50 kHz, warranted |
Frequency | Level |
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1 MHz | -100 dB |
10 MHz | -100 dB |
100 MHz | -85 dB |
400 MHz | -65 dB |
Frequency | Level | |
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0.25 Vpk-pk to 10 Vpk-pk | 25 Vpk-pk to 100 Vpk-pk | |
1 MHz | -85 dB | -70 dB |
10 MHz | -85 dB | -70 dB |
100 MHz | -75 dB | -55 dB |
300 MHz | -60 dB | -40 dB |
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Input Range (Vpk-pk) | <100 MHz, Full Bandwidth (dBc) | >100 MHz to <350 MHz, Full Bandwidth (dBc) |
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0.25 V | -70 | -66 |
0.5 V | -73 | -65 |
1 V | -74 | -66 |
2.5 V | -71 | -63 |
5 V | -69 | -60 |
Input Range (Vpk-pk) | <100 MHz, Full Bandwidth (dBc) | >100 MHz to <350 MHz, Full Bandwidth (dBc) |
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0.25 V | -70 | -62 |
0.5 V | -73 | -61 |
1 V | -73 | -62 |
2.5 V | -70 | -62 |
5 V | -70 | -60 |
Input Range (Vpk-pk) | <350 MHz, Full Bandwidth | <100 MHz, 150 MHz Filter | <10 MHz, 20 MHz, and/or 30 MHz Filter |
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0.25 V | 9.4 | 10.7 | 11.6 |
0.5 V | 9.5 | 10.9 | 11.7 |
1 V | 9.5 | 11.0 | 11.8 |
2.5 V | 9.6 | 11.1 | 11.9 |
5 V | 9.5 | 11.0 | 11.8 |
Input Range (Vpk-pk) | <100 MHz, Full Bandwidth (dBc) | >100 MHz to <250 MHz, Full Bandwidth (dBc) |
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0.25 V | -61 | -57 |
0.5 V | -56 | -50 |
1 V | -49 | -43 |
2.5 V | -59 | -55 |
5 V | -53 | -47 |
Input Range (Vpk-pk) | <50 MHz, Full Bandwidth (dBc) | 50 MHz to 250 MHz, Full Bandwidth (dBc) |
---|---|---|
0.25 V | -73 | -58 |
0.5 V | -68 | -50 |
1 V | -62 | -43 |
2.5 V | -70 | -56 |
5 V | -64 | -48 |
Input Range (Vpk-pk) | <250 MHz, Full Bandwidth | <100 MHz, 150 MHz Filter | <10 MHz, 20 Mhz, and/or 30 MHz Filter |
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0.25 V | 8.8 | 9.6 | 10.5 |
0.5 V | 8.1 | 9.8 | 11.1 |
1 V | 7.0 | 9.0 | 11.5 |
2.5 V | 8.6 | 9.5 | 10.4 |
5 V | 7.7 | 9.5 | 11.1 |
Input Range (Vpk-pk) | RMS Noise (% of Full Scale) |
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0.25 V | 0.045 |
0.5 V | 0.040 |
1 V | 0.035 |
2.5 V | 0.030 |
5 V | 0.030 |
Input Range (Vpk-pk) | RMS Noise (% of Full Scale) |
---|---|
0.25 V | 0.018 |
0.5 V | 0.018 |
1 V | 0.017 |
2.5 V | 0.017 |
5 V | 0.014 |
Input Range (Vpk-pk) | RMS Noise (% of Full Scale), Warranted |
---|---|
0.25 V | 0.110 |
0.5 V | 0.060 |
1 V | 0.050 |
2.5 V | 0.100 |
5 V | 0.060 |
10 V | 0.050 |
25 V | 0.080 |
50 V | 0.060 |
100 V | 0.050 |
Input Range (Vpk-pk) | RMS Noise (% of Full Scale) |
---|---|
0.25 V | 0.070 |
0.5 V | 0.050 |
1 V | 0.030 |
2.5 V | 0.100 |
5 V | 0.050 |
10 V | 0.030 |
25 V | 0.060 |
50 V | 0.040 |
100 V | 0.030 |
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Sample rate range, real-time[17] |
15.259 kS/s to 1 GS/s |
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Timebase frequency |
1.0 GHz |
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Sample clock jitter[18] |
500 fs RMS |
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Duty cycle tolerance |
45% to 55%, typical |
Source |
CLK IN (front panel SMB connector) |
Impedance |
50 Ω |
Coupling |
AC |
Frequency |
1.0 GHz |
Input voltage range, when configured as a sample clock |
632 mVpk-pk to 5 Vpk-pk (0 dBm to 18 dBm), typical |
Maximum input overload, when configured as a sample clock |
6 Vpk-pk |
Duty cycle tolerance |
45% to 55%, typical |
Sources |
CLK IN (front panel SMB connector) AUX 0 CLK IN (front panel MHDMR connector) |
Impedance |
50 Ω |
Coupling |
AC |
Frequency[19] |
10 MHz |
Input voltage range, when configured as a reference clock |
623 mVpk-pk to 5 Vpk-pk (0 dBm to 18 dBm), typical |
Maximum input overload, when configured as a reference clock |
6 Vpk-pk |
Supported triggers |
Reference (stop) trigger Reference (arm) trigger Start trigger Advance trigger |
Trigger types |
Edge Window Hysteresis Digital Immediate Software |
Trigger sources |
CH 0 CH 1 SMB PFI 0 AUX 0 PFI <0..7> PXI_Trig <0..6> Software |
Trigger delay |
from 0 ns to 2.25 × 1015 ns ((251 - 1) × Sample Clock Period ns) |
Dead time |
496 ns |
Hold off |
From dead time to 1.84 × 1019 ns ((264 - 1) × Sample Clock Period ns) |
Sources |
CH 0 CH 1 |
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Trigger accuracy[21] |
0.5% of FS |
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Trigger jitter[21] |
15 ps RMS |
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Minimum threshold duration[22] |
Sample clock period |
Connectors |
AUX 0 PFI <0..7> (front panel MHDMR connector) PFI 0 (front panel SMB connector) |
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Direction |
Bidirectional per channel |
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Direction control latency |
125 ns |
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Connector |
MHDMR |
Voltage output |
3.3 V ±10% |
Maximum current drive on +3.3 V |
200 mA |
Output impedance on +3.3 V |
<1 Ω |
Onboard memory size[24] |
1.5 GB |
Minimum record length |
1 sample |
Number of pretrigger samples |
Zero up to (Record Length - 1) |
Number of posttrigger samples |
Zero up to Record Length |
Maximum number of records in onboard memory[25] |
4,194,304 for 1.5 GB |
Channels | Bytes per Sample | Max Records per Channel | Record Length | Allocated Onboard Memory per Record |
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1 | 2 | 4,194,304 | 1 | 384 |
1 | 2 | 671,088 | 1,000 | 2,400 |
1 | 2 | 79,137 | 10,000 | 20,352 |
1 | 2 | 1 | 805,306,192 | 1,610,612,736 |
2 | 2 | 4,194,304 | 1 | 384 |
2 | 2 | 364,722 | 1,000 | 4,416 |
2 | 2 | 39,850 | 10,000 | 33,216 |
2 | 2 | 1 | 402,653,096 | 1,610,612,736 |
For information about memory sanitization, refer to the letter of volatility for your device, which is available at ni.com/manuals.
FPGA model |
Xilinx Kintex-7 XC7K410T FPGA |
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External calibration yields the following benefits:
All calibration constants are stored in nonvolatile memory.
This device was first supported in NI-SCOPE 16.1 and NI LabVIEW Instrument Design Libraries for Reconfigurable Oscilloscopes 16.1. NI LabVIEW Instrument Design Libraries for Reconfigurable Oscilloscopes is an IVI-compliant driver that allows you to configure, control, and calibrate the device. NI-SCOPE provides application programming interfaces for many development environments.
NI-SCOPE provides programming interfaces, documentation, and examples for the following application development environments:
LabVIEW Instrument Design Libraries for Reconfigurable Oscilloscopes allows the use of the LabVIEW FPGA Module to customize the device FPGA to create application-specific instrument designs.
When you install NI-SCOPE on a 64-bit system, you can monitor, control, and record measurements from the PXIe-5164 using InstrumentStudio.
InstrumentStudio is a software-based front panel application that allows you to perform interactive measurements on several different device types in a single program.
Interactive control of the PXIe-5164 was first available via InstrumentStudio in NI-SCOPE 18.1 and via the NI-SCOPE SFP in NI-SCOPE 16.1. InstrumentStudio and the NI-SCOPE SFP are included on the NI-SCOPE media.
NI Measurement & Automation Explorer (MAX) also provides interactive configuration and test tools for the PXIe-5164. MAX is included on the NI-SCOPE and NI LabVIEW Instrument Design Libraries for Reconfigurable Oscilloscopes media.
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NI-TClk is an API that enables system synchronization of supported PXI modules in one or more PXI chassis, which you can use with the PXIe-5164 and NI-SCOPE.
NI-TClk uses a shared Reference Clock and triggers to align the Sample Clocks of PXI modules and synchronize the distribution and reception of triggers. These signals are routed through the PXI chassis backplane without external cable connections between PXI modules in the same chassis.
Form factor |
PXI Express (x8 Gen 2) |
Slot compatibility |
PXI Express or hybrid |
DMA channels |
32 |
Dimensions |
3U, one-slot, PXI Express Gen 2 x8 module 21.26 cm × 12.88 cm × 2.0 cm (8.37 in × 5.07 in × 0.787 in) |
Weight |
460 g (16.2 oz) |
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Pollution Degree |
2 |
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Maximum altitude |
4,600 m (570 mbar) (at 25 °C ambient temperature) |
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Operating shock |
30 g, half-sine, 11 ms pulse |