These specifications apply to the PXIe-6570. When using the PXIe-6570 in the Semiconductor Test System, refer to the Semiconductor Test System Specifications.
Warranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty. Warranted specifications account for measurement uncertainties, temperature drift, and aging. Warranted specifications are ensured by design or verified during production and calibration.
The following characteristic specifications describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.
Specifications are valid under the following conditions unless otherwise noted.
Channel count |
32 |
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System channel count[1] |
256 |
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Large Vector Memory (LVM) |
128M vectors |
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Maximum allowable offset (DGS minus GND) |
±300 mV |
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Supported measurement range[2] |
-2 V to 7 V[3] |
Maximum vector rate |
100 MHz |
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Vector period range |
10 ns to 40 µs (100 MHz to 25 kHz) |
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Vector period resolution |
38 fs |
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Master clock source |
PXIe_CLK100[4] |
Sequencer clock domains |
One (independent sequencer clock domains on a single instrument not supported) |
Termination mode settings affect the termination applied to all non-driving pin states. Non-drive states include L, H, M, V, X, E, and potentially -. Refer to the Programmable input termination mode specification for more information.
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Number of time sets[8] |
31 |
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Edge placement resolution |
39.0625 ps |
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TDR deskew adjustment resolution |
39.0625 ps |
Signal type |
Single-ended, referenced to the DGS pin when connected. Otherwise referenced to GND. |
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Programmable levels |
VIH, VIL, VTERM |
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Maximum DC drive current |
±32 mA |
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Output impedance |
50 Ω |
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Rise/fall time, 20% to 80% |
1.2 ns, up to 5 V |
Signal type |
Single-ended, referenced to the DGS pin when connected. Otherwise referenced to GND. |
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Programmable levels |
VOH, VOL |
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High Z, 50 Ω to VTERM, Active Load |
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Leakage current |
<15 nA, in the High Z termination mode |
Signal type |
Single-ended, referenced to the DGS pin when connected. Otherwise referenced to GND. |
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Signal type |
Single-ended, referenced to the DGS pin when connected. Otherwise referenced to GND. |
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Range | Resolution | Accuracy |
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±2 µA | 60 pA | ±1% of range for Zone 1 of Figure 3, warranted |
±32 µA | 980 pA | |
±128 μA | 3.9 nA | |
±2 mA | 60 nA | |
±32 mA | 980 nA |
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Range | Resolution | Accuracy |
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±2 μA | 460 pA |
±1% of range for Zone 1 of Figure 4, warranted ±1.5% of range for Zone 2 of Figure 4, warranted |
±32 μA | 7.3 nA | |
±128 μA | 30 nA | |
±2 mA | 460 nA | |
±32 mA | 7.3 μA |
Refer to the following table for supported opcodes. Using matched and failed opcode parameters with multiple PXIe-6570 instruments requires the PXIe-6674T synchronization module. Other uses of flow-control opcodes with multiple PXIe-6570 instruments only require NI-TCLK synchronization.
Category | Supported Opcodes |
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Flow Control | |
Sequencer Flags and Registers | |
Signal | |
Digital Source and Capture |
Number of Clock Generators |
32 (one per pin) |
Clock Period Range |
6.25 ns to 40 us (160 MHz to 25 kHz)[12] |
Clock Period Resolution |
38 fs |
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Use the following equation to calculate the frequency counter error (ppm).
where
Refer to the following table for a few examples of common Clk100 timebase accuracies.
PXI Express Hardware Specification Revision 1.0 | PXIe-1085 Chassis | PXIe-6674T Override |
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100 µ (100 ppm) | 25 µ (25 ppm) | 80 n (80 ppb) |
PXIe slots |
2 |
Dimensions |
131 mm × 42 mm × 214 mm (5.16 in. × 1.65 in. × 8.43 in.) |
Weight |
920 g (32.45 oz.) |
The PXIe-6570 draws current from a combination of the 3.3 V and 12 V power rails. The maximum current drawn from each of these rails can vary depending on the PXIe-6570 mode of operation. The total power consumption will not exceed the input power specification.
Input power |
68 W |
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