Table Of Contents

Time Register Bus (Clock-Driven Logic)

Last Modified: August 4, 2018

Connects Time to the Register Bus.



LabVIEW FPGA resources used by Time, obtained from the Create Time node.


register instruction

specifies a read or write register instruction. This parameter is usually obtained from the register instruction parameter of the Process node. The source of this parameter defines the instances of the Register Bus library to which the Synchronization library instance is wired, and is communicated from the host.


read completion

Indicates whether the register read operation is complete and returns the data from the register read. Wire this parameter through either a shift register or a Feedback Node back to the read completion parameter on the Process node of the Register Bus.


ready for input

Indicates whether the node is ready to accept new input data in the next cycle. Use a Feedback Node to wire this parameter to the ready for output terminal of an upstream node.

Where This Node Can Run:

Desktop OS: none

FPGA: Supported

Web Server: Not supported in VIs that run in a web application

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