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Synchronize Signal Star (Clock-Driven Logic)

Last Modified: August 4, 2018

Synchronously realizes a signal over a star topology typically using PPS Trig. If this target is the master, it distributes edge on the specified FPGA I/O line on the next falling edge of the CPTR (when edge is high). If this target is not the master, it ignores edge. All targets, master or otherwise, also read the FPGA I/O line. The synchronized edge output goes high on the next CPTR edge after the edge is read from the FPGA I/O line.


The input edge should be a pulse. This is enforced by the node. There is a rising edge detector in the edge input. Additionally, after an edge is seen, another edge is not recognized until after the edge distribution completes. This means that the minimum time between edges for synchronization is one to two CPTR periods, depending on when the edge is seen within the CPTR period. Two physical connection topologies, bus and star, are supported. In the bus topology, all targets are connected to a common bus, usually the AUX I/O. In the star topology, the master is connected to all the slaves, usually with PPS TRIG, and also back to itself.


sync.resources in

Synchronization instance. sync.resources is obtained from the Create node.



Specifies whether to synchronize the input edge or not.


The sync.fpga io in may be floating until a target is specified as the master. enable should be FALSE until after the host Synchronization node executes to prevent erroneous outputs on synchronized edge.



Signal being synchronized. Because the first block this input encounters is a rising edge detector, the input signal edge is treated as a pulse.


sync.fpga io in

The FPGA I/O line to receive the synchronization signals on. This line is commonly the PPS Trig In line.


sync.resources out

The same instance that was passed in for sync.resources.


sync.fpga io signal out

The signal to send out over an FPGA I/O line. This line is commonly the PPS Trig Out line. Wire this output into an input of FPGA IO Out for Star.


synchronization delay

The number of clock cycles of delay that were added by synchronizing the input edge. This value is zero if enable is FALSE. If enable is TRUE, this value is valid only on the master target.


synchronized edge

The synchronized input edge if enable is TRUE.

Where This Node Can Run:

Desktop OS: none

FPGA: Supported

Web Server: Not supported in VIs that run in a web application

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