Table Of Contents

Advanced (Clock-Driven Logic)

Last Modified: August 4, 2018

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Aligns the targets participating in synchronization before synchronizing a signal without using an FPGA I/O line.
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Sends out the synchronization signals as needed for the star-topology-based synchronization.
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Aligns the participating targets connected to a common bus, typically AUX I/O, before synchronizing a signal.
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Aligns the participating targets in a star topology, typically connected using PPS Trig, before synchronizing a signal.
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Synchronously realizes a signal over a bus topology typically using AUX I/O.
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Synchronously realizes a signal over a star topology typically using PPS Trig.

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