Table Of Contents

Registers (Clock-Driven Logic)

Last Modified: August 4, 2018

Sets/gets the configuration values for the Synchronization nodes by connecting it to the Register Bus.


register instruction

A read or write register instruction. This parameter is usually obtained from the register instruction parameter of the Process node. The source of this parameter defines the Register Bus objects to which the Synchronization node is wired, and it is communicated from the host.



Synchronization instance. sync.resources is obtained from the Create node.


ready for input

Boolean that indicates whether the node is ready to accept new input data in the next cycle. Use a Feedback Node to wire this parameter to the ready for output input of an upstream node.


read completion

Indicates whether the register read operation is complete and returns the data from the register read. Wire this parameter through either a shift register or a Feedback Node back to the read completion parameter on the Process node of the Register Bus.

Where This Node Can Run:

Desktop OS: none

FPGA: Supported

Web Server: Not supported in VIs that run in a web application

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