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FPGA IO Out for Star (Clock-Driven Logic)

Last Modified: August 4, 2018

Sends out the synchronization signals as needed for the star-topology-based synchronization.

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sync.fpga io out

The FPGA I/O line to send the signal out on.

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sync.fpga io signal out

Signal needed for the synchronization library from Host Align Star or Synchronize Signal Star. Only one sync.fpga io signal out should be TRUE at a time (all the inputs are Red).

Where This Node Can Run:

Desktop OS: none

FPGA: Supported

Web Server: Not supported in VIs that run in a web application


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