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FPGA Align (Clock-Driven Logic)

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Last Modified: August 4, 2018

Aligns the targets participating in synchronization before synchronizing a signal without using an FPGA I/O line.

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sync.resources in

Synchronization instance. sync.resources is obtained from the Create node.

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common reference

The "start" signal used by the measurement logic. When you use FPGA Align, the common reference must be the same clock to which the FPGA Clock of the target is locked.

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clock x2

Measurement clock used by the measurement logic. This clock must run at twice the rate of the FPGA Clock, which is the clock that drives the clock-driven loop (CDL) that this node is in. This clock must also derive from the FPGA Clock so that it has a fixed phase relationship. This clock is commonly Data Clock x2.

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sync.resources out

The same instance that was passed in for sync.resources.

Choose Host Align or FPGA Align

You can choose from two flavors of alignment, Host Align or FPGA Align. The two flavors produce the same quality of synchronization, but they differ in requirements, repeatability, and versatility of operation. When you use FPGA Align, the clock-driven loop (CDL) rate that this node is in must be an integer multiple of the sync.common reference rate, and the CDL Clock must have a fixed phase relationship to the common reference. Because each target performs its alignment independently, FPGA Align does not require an FPGA I/O line. It is also possible to use FPGA Align without host interaction. FPGA Align has 100 percent repeatability if the target-to-reference clock phase relationship is low and does not change. When you use Host Align, the CDL rate may be arbitrary, yet still must have a fixed phase relationship to the other targets. The CPTR period may also be arbitrary. This alignment process is coordinated by the host and requires an FPGA I/O line for orchestration. Host Align has 100 percent repeatability; if the hardware configuration remains constant, so will the level of synchronization.

Two Physical Connection Topologies

Two physical connection topologies, bus and star, are supported. In the bus topology, all targets are connected to a common bus, usually the AUX I/O. In the star topology, the master is connected to all the slaves, usually with PPS Trig, and also back to itself.

Where This Node Can Run:

Desktop OS: none

FPGA: Supported

Web Server: Not supported in VIs that run in a web application

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