Table Of Contents

Synchronization Clock Properties

Version:
    Last Modified: September 11, 2019

    Name Description
    Sync Clk Src (Back) Specifies the synchronization clock source for the rear zone (PXI_Trig, PXI_Star, and PXIe_DStarB) terminals.
    Sync Clk Src (Front) Specifies the synchronization clock source for the front zone (PFI and PFI_LVDS) terminals.
    Clk Divisor 1 Specifies or returns the value for the first clock divisor.
    Clk Divisor 2 Specifies or returns the value of the second clock divisor.
    PFI0 Freq Ref Specifies or returns the frequency reference, in MHz, for the PFI0 terminal.
    PXI_Trig Reset Sync Clk Specifies or returns which PXI_Trig terminal contains the update pulse used to reset the synchronization clock dividers.
    PXI_Trig Reset DDS Cntrs Specifies or returns whether the DDS clock dividers should reset when the device receives an update pulse on the PXI_Trig line specified in the Reset Synchronization Clock PXI_Trig Line parameter.
    Reset PXI_Clk10 Counters on PXI_Trig Specifies or returns whether or not PXI_Clk10 clock dividers should reset when the device receives an update pulse on a PXI_Trig line.
    PXI_Trig Reset PFI0 Cntrs Specifies or returns whether or not the PFI0 clock dividers should reset when the device receives an update pulse on a PXI_Trig.

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