Specifies whether the connection between ClkIn and PXI_Clk10 should use the PLL circuit.
If this Boolean value is set to TRUE, the PLL will be used to lock to the frequency at ClkIn when connecting to PXI_Clk10. You must set this property before connecting the clock to PXI_Clk10_In.
Long Name: Use PLL?
Where This Property Is Available:
Desktop OS: Windows
FPGA: Not supported
Web Server: Not supported in VIs that run in a web application