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PXI_Trig Reset Sync Clk

Version:
    Last Modified: September 9, 2019

    Specifies or returns which PXI_Trig terminal contains the update pulse used to reset the synchronization clock dividers.

    The default is none. You must set this value before you can reset synchronization clock dividers using an update pulse on a PXI_Trig line.

    spd-note-note
    Note  
    • This property is supported only on signal-based devices.
    • This property is unsupported on the PXIe-6674T.

    Data type: datatype_icon

    Long Name: PXI_Trig Reset Sync Clk

    Class: Synchronization Clock

    Permissions: Read/Write

    Where This Property Is Available:

    Desktop OS: Windows

    FPGA: Not supported

    Web Server: Not supported in VIs that run in a web application


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