Specifies or returns which PXI_Trig terminal contains the update pulse used to reset the synchronization clock dividers.
The default is none. You must set this value before you can reset synchronization clock dividers using an update pulse on a PXI_Trig line.
Data type:
Where This Property Is Available:
Desktop OS: Windows
FPGA: Not supported
Web Server: Not supported in VIs that run in a web application