Table Of Contents
PXI_Trig Reset PFI0 Cntrs
Version:
Last Modified: September 9, 2019
Specifies or returns whether or not the PFI0 clock dividers should reset when the device receives an update pulse on a PXI_Trig.
You can specify which PXI_Trig line contains the update pulse using the Reset Synchronization Clock PXI_Trig Line parameter of the niSync Property Node. If TRUE, the PFI0 dividers reset on the rising edge of the update pulse.
Data type:
Where This Property Is Available:
Desktop OS: Windows
FPGA: Not supported
Web Server: Not supported in VIs that run in a web application