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PXI_Trig Reset PFI0 Cntrs

Version:
    Last Modified: September 9, 2019

    Specifies or returns whether or not the PFI0 clock dividers should reset when the device receives an update pulse on a PXI_Trig.

    You can specify which PXI_Trig line contains the update pulse using the Reset Synchronization Clock PXI_Trig Line parameter of the niSync Property Node. If TRUE, the PFI0 dividers reset on the rising edge of the update pulse.

    spd-note-note
    Note  
    • This property is supported only on signal-based devices.
    • This property is not supported by the PXIe-6674T.

    Data type: datatype_icon

    Long Name: PXI_Trig Reset PFI0 Cntrs

    Class: Synchronization Clock

    Permissions: Read/Write

    Where This Property Is Available:

    Desktop OS: Windows

    FPGA: Not supported

    Web Server: Not supported in VIs that run in a web application


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