Table Of Contents

Clk10 Phase Adjust

Version:
Last Modified: September 9, 2019

Specifies or returns the phase voltage between an external clock and PXI_Clk10 when you are using the PLL circuit to lock PXI_CLK10 to an external reference clock.

You can minimize the time between rising edges of PXI_CLK10 and the external reference clock using this parameter.

Data type: datatype_icon

Long Name: Clk10 Phase Adjust

Class: Calibration

Permissions: Read/Write

Where This Property Is Available:

Desktop OS: Windows

FPGA: Not supported

Web Server: Not supported in VIs that run in a web application


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