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ClkOut Gain Enable

Version:
Last Modified: September 9, 2019

Increases the amplitude of the ClkOut terminal.

Set this property to TRUE to increase the amplitude of the ClkOut terminal from 1 peak-to-peak volt to 2.5 peak-to-peak volts. Enable this property if you are distributing a clock between chassis to give the clock enough gain to reach its destination. Set the property to FALSE to return the amplitude to 1 peak-to-peak volt.

Data type: datatype_icon

Long Name: ClkOut Gain Enable

Class: Clock

Permissions: Read/Write

Where This Property Is Available:

Desktop OS: Windows

FPGA: Not supported

Web Server: Not supported in VIs that run in a web application


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