Increases the amplitude of the ClkOut terminal.
Set this property to TRUE to increase the amplitude of the ClkOut terminal from 1 peak-to-peak volt to 2.5 peak-to-peak volts. Enable this property if you are distributing a clock between chassis to give the clock enough gain to reach its destination. Set the property to FALSE to return the amplitude to 1 peak-to-peak volt.
Long Name: ClkOut Gain Enable
Where This Property Is Available:
Desktop OS: Windows
FPGA: Not supported
Web Server: Not supported in VIs that run in a web application