Table Of Contents
Clk Divisor 1
Version:
Last Modified: September 9, 2019
Specifies or returns the value for the first clock divisor.
Use this number to divide the full-speed synchronization clock and produce Divided Clock 1. The value must be a power of two between 2 and 512.
Data type:
Where This Property Is Available:
Desktop OS: Windows
FPGA: Not supported
Web Server: Not supported in VIs that run in a web application