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Clk Divisor 1

Version:
    Last Modified: September 9, 2019

    Specifies or returns the value for the first clock divisor.

    Use this number to divide the full-speed synchronization clock and produce Divided Clock 1. The value must be a power of two between 2 and 512.

    Data type: datatype_icon

    Long Name: Clk Divisor 1

    Class: Synchronization Clock

    Permissions: Read/Write

    Where This Property Is Available:

    Desktop OS: Windows

    FPGA: Not supported

    Web Server: Not supported in VIs that run in a web application


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