Use Clock properties to specify or return information about the PLL circuit, front panel connectors, and PXI_Clk10.
| Name | Description |
|---|---|
| PLL Frequency | Specifies or returns the frequency of the clock the PLL circuit should lock to. |
| Use PLL? | Specifies whether the connection between ClkIn and PXI_Clk10 should use the PLL circuit. |
| PLL Locked? | Returns whether or not the PXI_Clk10 PLL is currently locked to a signal at the ClkIn terminal. |
| PXI_Clk10 Present? | Returns whether or not the PXI_Clk10 signal is present on the PXI backplane. |
| ClkOut Gain Enable | Increases the amplitude of the ClkOut terminal. |
| Disable ClkIn Attenuation | Specifies whether or not to attenuate the signal at ClkIn. |