Table Of Contents
Defining NI-Sync Trigger Terminals
Version:
Last Modified: September 15, 2017
Descriptions of trigger terminals you can connect with NI-Sync functions.
Using niSync Connect Trigger Terminals, you can route triggers between modules, synchronize triggers to different synchronization clocks, and export clock signals along some trigger lines. The function uses trigger terminals to pass trigger signals from place to place. Use the following table to determine what hardware lines each source and destination terminal refers to.
| Trigger Terminal | Description |
|---|---|
| PXI_Trig<n> | The basic trigger lines of your PXI or PXIe chassis. PXI triggers go to and from all slots in the chassis—though the signals do not reach all slots at the same time—and all modules receive the same PXI triggers, so PXI_Trig0 is the same for Slot 3 as it is for Slot 4, and so on. |
| PXI_Star<n> | The star trigger lines of your PXI or PXIe chassis. Each trigger line is a dedicated connection between the system timing slot and one other slot. Star triggers are all of equal length, so signals routed via star trigger should reach their destinations at the same time if they were sent at the same time. |
| PFI<n> | The PFI connectors on the front panel of the module. You can use PFI connectors to route triggers between multiple chassis or devices. |
| PFI_LVDS<n> | The PFI low voltage differential signaling (LVDS) input/output connectors on the front panel of the device. PFI LVDS lines consist of paired PFI lines and can be used to route timing and triggering signals between multiple PXIe chassis at high speeds. You can achieve faster speeds when using an LVDS line compared to a single-ended PFI line. Signals on PFI LVDS lines use the standard PFI synchronization clock. |
| Ground (Source Only) | The Ground source continuously outputs a logic low signal, unless you invert it with niSync Connect Trigger Terminals. |
| Full Speed Clock (Source Only) | The full speed synchronization clock signal of the destination terminal zone. Use this source to send a full-speed clock signal along a trigger line (for example, to route a PXI_Clk10 clock signal to a PFI line). |
| Divided Clock 1 (Source Only) | The first divided clock signal of the destination terminal zone. This source divides the synchronization clock of the destination terminal by the value you specify in the Clock Divisor 1 property and uses the result as the trigger source. Use this source to send a divided clock signal along a trigger line (for example, to route a divided DDS signal to a PXI_Star line). |
| Divided Clock 2(Source Only) | The second divided clock signal of the destination terminal zone. This source divides the synchronization clock of the destination terminal by the value you specify in the Clock Divisor 2 property and uses the result as the trigger source. Use this source to send a divided clock signal along a trigger line (for example, to route a divided PXI_Clk10 signal to a PXI_Star line). |
| ClkIn (Source Only) | The ClkIn connector on the front panel of your device. Use this terminal source to route triggers from an external device. |
| PXIe_DStarB<n> | The differential star trigger lines of your PXIe chassis. Use PXIe_DStarB lines to send trigger signals from the system timing slot to a peripheral slot of the chassis. |
| PXIe_DStarC<n> | The differential star trigger lines of your PXIe chassis. Use PXIe_DStarC lines to send trigger and clock signals from a peripheral slot to the system timing slot of the chassis. |
