Connecting an External Reference Clock to a PXI Backplane Clock

Use the following procedure to connect an external reference clock to the backplane clock of a PXI chassis. You can do this to synchronize a backplane clock to an external reference clock. Alternately, you can discipline the 10 MHz backplane clock with an OCXO on a timing and synchronization module installed in the PXI chassis.

• NI-Sync 17.0 or above.
• An external reference clock.

1. Connect the external 10 MHz reference source to the CLKIN connector on the device in the system timing slot of the PXI chassis.

Program the Route from ClkIn to PXI_Clk10_IN

2. Call Initialize (niSync)to set up a handle for the device.
3. This step is only necessary if you are using a PXI-6674T in the system timing slot. Set the Use PLL? property to False.
   1. Place niSync Properties on the diagram.
   2. Select Clock from the drop-down menu and select Use PLL? as the first property.
   3. Right-click Use PLL? and select Change to Write.
   4. Connect a Boolean constant to Use PLL? and set it to False.
   The PXI-6674T will not use a phase-locked loop to sync with PXI_Clk10_In.
4. Place Connect Clock Terminals. Set the source terminal to ClkIn and the destination terminal to PXI_Clk10_In. The external reference clock connected to ClkIn is now routed to the PXI backplane clock.
5. Place Close on the diagram to close the niSync session.