Use the following procedure to connect an external reference clock to the backplane clock of a PXI chassis. You can do this to synchronize a backplane clock to an external reference clock. Alternately, you can discipline the 10 MHz backplane clock with an OCXO on a timing and synchronization module installed in the PXI chassis.
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NI-Sync 17.0 or above.
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An external reference clock.
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Connect the external 10 MHz reference source to the CLKIN connector on the device in the system timing slot of the PXI chassis.
Program the Route from ClkIn to PXI_Clk10_IN
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Call
Initialize (niSync)to set up a handle for the device.
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This step is only necessary if you are using a PXI-6674T in the system timing slot. Set the
Use PLL?
property to
False.
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Place
niSync Properties
on the diagram.
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Select
Clock
from the drop-down menu and select
Use PLL?
as the first property.
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Right-click
Use PLL?
and select
Change to Write.
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Connect a Boolean constant to
Use PLL?
and set it to
False.
The PXI-6674T will not use a phase-locked loop to sync with PXI_Clk10_In.
-
Place
Connect Clock Terminals. Set the
source terminal
to
ClkIn
and the
destination terminal
to
PXI_Clk10_In.
The external reference clock connected to ClkIn is now routed to the PXI backplane clock.
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Place
Close
on the diagram to close the niSync session.