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Use PLL?

Last Modified: September 9, 2019

Specifies whether the connection between ClkIn and PXI_Clk10 should use the PLL circuit.

If this Boolean value is set to TRUE, the PLL will be used to lock to the frequency at ClkIn when connecting to PXI_Clk10. You must set this property before connecting the clock to PXI_Clk10_In.

Data type: datatype_icon

Long Name: Use PLL?

Class: Clock

Permissions: Read/Write

Where This Property Is Available:

Desktop OS: Windows

FPGA: Not supported

Web Server: Not supported in VIs that run in a web application

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