Table Of Contents
Route Signal Out (G Dataflow)
Routes various signals to the backplane trigger lines or front panel terminals.
The waveform generator must not be in the Generating state when you call this node.
route signal from
The source of the signal to route.
You can clear a previously routed signal by routing NONE to the destination terminal.
| Name | Value | Description |
|---|---|---|
| NONE | 0 | A previously routed signal is cleared, and no source is sent to the destination terminal. |
| MARKER | 1 | The node uses a marker event as the source of the signal to route. |
| SYNC OUT | 2 | The node uses the SYNC OUT source as the signal to route. |
| OUT START TRIGGER | 3 | The node uses a Start Trigger as the source of the signal to route. |
| BOARD CLOCK | 4 | The node uses a 20 MHz source derived from the Sample Clock Timebase as the signal to route. |
| SYNCHRONIZATION | 5 | The node uses the synchronization source as the signal to route. |
| SOFTWARE TRIGGER | 6 | The node routes a signal generated by Send Software Edge Trigger or niFgen_SendSoftwareEdgeTrigger. |
| REF IN | 7 | The node uses the REF IN front panel connector as the source of the signal to route. |
| PXI_CLK10 | 8 | The node uses the 10 MHz PXI backplane clock as the source of the signal to route. |
| PXI STAR | 9 | The node uses the PXI_Star trigger line from the PXI backplane as the source of the signal to route. |
| PFI 0 | 10 | The node uses the PFI 0 front panel connector as the source of the signal to route. |
| PXI_Trig0 | 11 | The node uses the RTSI 0 PCI backplane trigger line or PXI_Trig 0 PXI backplane trigger line as the source of the signal to route. |
| PXI_Trig1 | 12 | The node uses the RTSI 1 PCI backplane trigger line or PXI_Trig 1 PXI backplane trigger line as the source of the signal to route. |
| PXI_Trig2 | 13 | The node uses the RTSI 2 PCI backplane trigger line or PXI_Trig 2 PXI backplane trigger line as the source of the signal to route. |
| PXI_Trig3 | 14 | The node uses the RTSI 3 PCI backplane trigger line or PXI_Trig 3 PXI backplane trigger line as the source of the signal to route. |
| PXI_Trig4 | 15 | The node uses the RTSI 4 PCI backplane trigger line or PXI_Trig 4 PXI backplane trigger line as the source of the signal to route. |
| PXI_Trig5 | 16 | The node uses the RTSI 5 PCI backplane trigger line or PXI_Trig 5 PXI backplane trigger line as the source of the signal to route. |
| PXI_Trig6 | 17 | The node uses the RTSI 6 PCI backplane trigger line or PXI_Trig 6 PXI backplane trigger line as the source of the signal to route. |
| PXI_Trig7 | 18 | The node uses the RTSI 7 PCI backplane trigger line or PXI_Trig 7 PXI backplane trigger line as the source of the signal to route. |
| RTSI CLOCK | 19 | The node uses the RTSI_CLOCK line from the PCI backplane as the source of the signal to route. |
| CLOCK OUT | 20 | The node uses the CLOCK Out front panel connector as the source of the signal to route. |
| PLL REF SOURCE | 21 | The node uses the PLL REF front panel connector as the source of the signal to route. |
| UPDATE CLOCK | 22 | The node uses the Update Clock as the source of the signal to route. |
| ONBOARD REF CLOCK | 23 | The node uses the onboard Reference Clock as the source of the signal to route. |
session in
Handle that identifies your instrument session previously allocated by Initialize With Channels.
error in
Error conditions that occur before this node runs.
The node responds to this input according to standard error behavior.
Standard Error Behavior
Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.
Default: No error
channel name
Name of the waveform generator channel that the node uses.
route signal to
The destination of the signal to route.
| Name | Value | Description |
|---|---|---|
| PXI_Trig0 | 0 | The node routes the signal to the RTSI 0 PCI backplane trigger line or PXI_Trig 0 PXI backplane trigger line. |
| PXI_Trig1 | 1 | The node routes the signal to the RTSI 1 PCI backplane trigger line or PXI_Trig 1 PXI backplane trigger line. |
| PXI_Trig2 | 2 | The node routes the signal to the RTSI 2 PCI backplane trigger line or PXI_Trig 2 PXI backplane trigger line. |
| PXI_Trig3 | 3 | The node routes the signal to the RTSI 3 PCI backplane trigger line or PXI_Trig 3 PXI backplane trigger line. |
| PXI_Trig4 | 4 | The node routes the signal to the RTSI 4 PCI backplane trigger line or PXI_Trig 4 PXI backplane trigger line. |
| PXI_Trig5 | 5 | The node routes the signal to the RTSI 5 PCI backplane trigger line or PXI_Trig 5 PXI backplane trigger line. |
| PXI_Trig6 | 6 | The node routes the signal to the RTSI 6 PCI backplane trigger line or PXI_Trig 6 PXI backplane trigger line. |
| RTSI CLOCK | 7 | The node routes the signal to the RTSI_CLOCK PCI backplane line. |
| REF OUT | 8 | The node routes the signal to the REF OUT front panel connector. |
| PFI 0 | 9 | The node routes the signal to the PFI 0 front panel connector. |
| PXI_Trig7 | 10 | The node routes the signal to the RTSI 7 PCI backplane trigger line or PXI_Trig 7 PXI backplane trigger line. |
| PFI 1 | 11 | The node routes the signal to the PFI 1 front panel connector. |
| PFI 4 | 12 | The node routes the signal to the PFI 4 line on the DIGITAL DATA & CONTROL (DDC) front panel connector. |
| PFI 5 | 13 | The node routes the signal to the PFI 5 line on the DIGITAL DATA & CONTROL (DDC) front panel connector. |
| PXI STAR | 14 | The node routes the signal to the PXI_Star trigger line on the PXI backplane. |
session out
Reference to your instrument session to wire to the next node.
error out
Error information.
The node produces this output according to standard error behavior.
Standard Error Behavior
Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.
Where This Node Can Run:
Desktop OS: Windows
FPGA: Not supported
Web Server: Not supported in VIs that run in a web application