Adjust Sample Clock Relative Delay (G Dataflow)

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Last Modified: July 24, 2019

Delays (or phase shifts) the Sample Clock, which delays the output of the waveform generator.

The delay takes effect immediately after this node is called. Delaying the Sample Clock can be useful when lining up the output of multiple instruments or when intentionally phase shifting the output relative to a fixed reference, such as the PLL Reference Clock.

Programming Patterns

Calling this node after calling NI-TClk Synchronize breaks synchronization.

session in

Handle that identifies your instrument session previously allocated by Initialize With Channels.

error in

Error conditions that occur before this node runs.

The node responds to this input according to standard error behavior.

Standard Error Behavior

Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.

error in does not contain an error	error in contains an error

If no error occurred before the node runs, the node begins execution normally. If no error occurs while the node runs, it returns no error. If an error does occur while the node runs, it returns that error information as error out.	If an error occurred before the node runs, the node does not execute. Instead, it returns the error in value as error out.

Default: No error

adjustment time

Amount of time to adjust the Sample Clock delay in seconds (s).

adjustment time can be positive or negative, but it must be less than or equal to the Sample Clock period.

session out

Reference to your instrument session to wire to the next node.

error out

Error information.

The node produces this output according to standard error behavior.

Standard Error Behavior

error in does not contain an error	error in contains an error

If no error occurred before the node runs, the node begins execution normally. If no error occurs while the node runs, it returns no error. If an error does occur while the node runs, it returns that error information as error out.	If an error occurred before the node runs, the node does not execute. Instead, it returns the error in value as error out.

Delaying an External Sample Clock

To delay an external Sample Clock, set the Sample Clock Absolute Delay property.

Where This Node Can Run:

Desktop OS: Windows

FPGA: Not supported

Web Server: Not supported in VIs that run in a web application

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