Specifies the voltage limit high, or high clamp voltage (VCH), and voltage limit low, or low clamp voltage (VCL), for the specified pins when forcing current.
You must call the niDigital PPMU Source node for changes to the PPMU configuration to take effect, even if the PPMU is already sourcing.
Instrument session obtained from the niDigital Initialize with Options node.
List of channel names or list of pins. Do not pass a mix of channel names and pin names.
An empty string denotes all digital pattern instrument channels.
Specify channel names using the form PXI1Slot3/0,2-3 or PXI1Slot3/0,PXI1Slot3/2-3, where PXI1Slot3 is the instrument resource name and 0, 2, 3 are channel names.
To specify channels from multiple instruments, use the form PXI1Slot3/0,PXI1Slot3/2-3,PXI1Slot4/2-3. The instruments must be in the same chassis.
Site Considerations and Syntax
Error conditions that occur before this node runs.
The node responds to this input according to standard error behavior.
Standard Error Behavior
Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.
Default: No error
Handle that identifies the session in all subsequent NI-Digital node calls.
Error information.
The node produces this output according to standard error behavior.
Standard Error Behavior
Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.
When forcing current by setting the niDigital PPMU Configure Output node to DC Current, the voltage is clamped to the specified voltage limits. Select the smallest voltage limits appropriate for the DUT.
If the voltage required by the DUT exceeds the specified voltage limits, the current output may not meet the specified current level. Choose larger voltage limits as needed and appropriate for the DUT.
Where This Node Can Run:
Desktop OS: Windows
FPGA: Not supported
Web Server: Not supported in VIs that run in a web application