Table Of Contents

Pattern Responses to Comparisons

Last Modified: November 23, 2020

Comparisons evaluate the output of the DUT at the strobe edge you specify for the time set of the vector. Failures for a vector result when any DUT response on any pin on any cycle does not match the expected value. All failures are logically combined into one matched or failed condition the sequencer can use. This functionality spans multiple digital pattern instruments when you use a PXIe-6674T configured to aggregate failure information. The sequencer executes vectors from memory, which includes information about the expected states of each pin. The delay of the vectors passing through stimulus conditioning circuitry, cabling/interconnect delays to and from the DUT, DUT response delays, and response conditioning circuitry affect the failure or match evaluation in a conditional jump or call in the pattern. The required delay for a failure or match evaluation in the pattern is 80 cycles for single and multiple digital pattern instruments in the test system.

Failures

To use a comparison result for a conditional jump in the pattern based on a failure, specify the L, H, V, M, or E pin states for the pins to compare and use the failed or !failed parameter of the jump_if or exit_loop_if opcode to execute the pattern in response to the evaluation. Because of the pipeline latency, at least 80 cycles must pass between the vector on which you specify the comparison to the vector on which you use the jump_if or exit_loop_if opcode. If any comparison on any pin results in a failure, the failed result remains true for all subsequent vectors until the next pattern burst clears it.

Matches

Use the match opcode on a vector to evaluate parameters on specific pins. Specify the L, H, V, M, or E pin states for the pins to compare. For example, if a DUT has a PLL_Locked and a Ready output and you want to wait until both outputs assert, specify H as the pin state for these pins, set all other pins in the pattern to X, and loop the pattern until the PLL_Locked and the Ready pins both match H, at which point the vector is flagged as a match. For example:

pattern match_loop(PLL_Locked, Ready)
{
set_loop(1000)                                         sample_timeset X X; // Set the timeout to 1,000 iterations.
repeat(80), match                                      sample_timeset H H; // Repeat the required minimum number of cycles to wait.
loop_begin: exit_loop_if(matched, loop_exit), match    sample_timeset H H;
end_loop(loop_begin), match                            sample_timeset H H;
jump(timeoutPattern)                                   sample_timeset X X; //If this vector executes, the loop timed out.
loop_exit: halt                                        sample_timeset X X; //Start of the pattern to execute after the match.
...
}

To use a comparison result for a conditional jump in the pattern based on a match, use the matched or !matched parameter of the jump_if or exit_loop_if opcode to execute the pattern in response to the evaluation. Because of the pipeline latency, exactly 80 cycles must pass between the vector on which you specify the comparison to the vector on which you use the jump_if or exit_loop_if opcode. All comparisons on all pins must match to result in a match. The match result represents the evaluation from the vector that executed exactly 80 cycles ago.


Recently Viewed Topics