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Timing Response Modes

Last Modified: January 31, 2020

Digital I/O and DAQ devices typically use the single-cycle timing response mode, meaning the device responds to an external signal by the next active sample clock edge.

Devices that support the pipelined timing response mode, such as the PCIe-6536 and PCIe-6537, can respond to an external signal a few sample clock edges later. This mode uses a source-synchronous clock scheme, which simultaneously returns the clock and data to the acquiring device. With a source-synchronous data transfer, you can acquire and generate data at much higher rates than with single-cycle timing response mode.

With the pipelined timing response mode, you can configure external sample clocks, but the sample clock must be free-running and started before the task commits. If you export the sample clock, the export occurs during a task commit. As with other events, when the task uncommits, the signal remains exported.

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