Table Of Contents

Buffered Pulse Generation

Last Modified: January 31, 2020

You can specify the size of the buffer by calling the DAQmx Configure Buffer function/VI, by specifying the buffer size attribute/property in the buffer property node, or by writing a number of pulse specifications using the DAQmx Write Counter MultiPoint function/VI before starting the task. This is ideal for applications that require pulse-width modulation, such as proportional integral derivative (PID) loop control applications. An example of an Implicit buffered generation would look like the following:

The high and low times provided in the Create Channel function/VI are ignored in this case.

If you do not use a software buffer, all pulses generated will be the same, unless you update the high time and low time while the application is running. This will cause the pulse specifications to be software timed and change on-demand.

You can use the same attributes/properties that create the channel to update the pulse specifications of the pulse train generation. Because you need two attributes/properties to specify the pulse specifications of the pulse train, the specifications only update when you set one of the two. For example, if you specify the pulse generation in terms of frequency, the frequency and duty cycle control the specifications of the generation. However, the pulse specifications only update when you set the frequency attribute/property. The same is true when you specify pulse generation in terms of time or ticks; the low time and low ticks control when the pulse specifications update. When updating the pulse specifications of the pulse generation, a complete period of the current specification generates before the new pulse specification takes effect. Updating the pulse specifications while running is not supported on buffered pulse train generation.

In some devices, such as M Series, E Series, and S Series devices, generating finite pulse trains requires the use of paired counters. In devices that require paired counters on a finite pulse train generation, the first counter (for example, Counter 0) generates a pulse of desired width. The second counter (Counter 1) generates the pulse train, which is gated by the pulse of the first counter. The routing is done internally. The following illustration shows a two counter finite pulse train timing diagram.


STC3-based devices, such as X Series devices, do not require paired counters.

Recently Viewed Topics