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Reference Clock Synchronization

Last Modified: January 31, 2020

Reference Clock synchronization is the most flexible and powerful synchronization method available on supported devices. Reference Clock synchronization allows you to synchronize all timing for the synchronized devices, even at different rates and regardless of subsystem, in that clocks derived from the Reference Clock start and remain in phase. Derived clocks with a slower frequency than the Reference Clock are not in phase. For counter operations, Reference Clock synchronization ensures the counter timebases remain synchronized without drift, or in phase if the application requires different counter timebase frequencies.

When using Reference Clock synchronization, a device does not directly use a clock from another device in place of an onboard clock. Instead, all devices synchronize their onboard oscillators to a common reference signal using a phase-locked loop. Each device then derives other clocks from the synchronized oscillators. You must share a Start Trigger for the derived clocks to start in phase.

For PXI devices, the reference signal is typically a 10 MHz clock on the chassis backplane ( PXI_Clk10). For PXI Express devices, the reference signal is typically a 100 MHz clock on the chassis backplane ( PXIe_Clk100).


Always use one of the PXI or PXI Express chassis backplane clocks, if possible. Using a clock from another device results in skew due to the time required for the signal to travel from one device to the other.

PXI or PXI Express chassis backplane clocks might provide different accuracy than the onboard oscillator of a device. For example, the PXIe-1062Q chassis has 25 ppm clock accuracy, while the PXI-6259 has 50 ppm clock accuracy.

For PCI and PCI Express devices, that reference signal is a clock from another device (typically 10MHzRefClk). Use the RefClk.Src attribute/property to specify the terminal of the reference signal for a given task. Set RefClk.Src to OnboardClock on the master device to lock to the onboard oscillator, rather than use it directly. Locking to the onboard oscillator helps to equalize skew between the master and slave devices.

Even though Reference Clock synchronization minimizes or eliminates skew in the clocks, the shared Start Trigger must travel from the master device to the slave devices, resulting in skew. Some devices allow you to correct for that skew.

Some devices use a Master Timebase instead of a Reference Clock, thus they use Master Timebase synchronization. Reference Clock synchronization also requires you to share multiple signals and reserve multiple RTSI or PXI trigger lines for those signals. For Sample Clock-timed applications where all devices run at the same rate, you can use Sample Clock synchronization to eliminate the need for a shared Start Trigger, thus the additional RTSI/PXI line. You can also use Sample Clock synchronization to synchronize devices that use a Master Timebase with devices that use a Reference Clock.

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