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DAQmx Timing (Burst Import Clock) (G Dataflow)

Last Modified: September 18, 2017

Configures when the DAQ device transfers data to a peripheral device, using an imported sample clock to control burst handshake timing.


task in

task in is the name of the task that the operation applies.


sample clock rate

sample clock rate specifies in hertz the rate of the Sample Clock.


sample clock source

sample clock source specifies the source terminal of the Sample Clock. Leave this input unwired to use the default onboard clock of the device.


sample clock active edge

sample clock active edge specifies on which edges of Sample Clock pulses to acquire or generate samples.

Name Description

Acquire or generate samples on falling edges of the Sample Clock.


Acquire or generate samples on rising edges of the Sample Clock.


error in

error in describes error conditions that occur before this node runs. This input provides standard 'error in' functionality.


sample mode

sample mode specifies if the task acquires, or generates samples continuously, or if it acquires or generates a finite number of samples.

Name Description
Continuous Samples

Acquire or generate samples until DAQmx Stop Task runs.

Finite Samples

Acquire or generate a finite number of samples.

Hardware Timed Single Point

Acquire or generate samples continuously using hardware timing without a buffer. Hardware timed single point sample mode is supported only for the sample clock and change detection timing types.


samples per channel

samples per channel specifies the number of samples to acquire, or generate for each channel in the task, if sample mode is Finite Samples. If sample mode is Continuous Samples, NI-DAQmx uses this value to determine the buffer size. This node returns an error if the specified value is negative.


pause when

pause when specifies whether the task pauses while the trigger signal is high or low.

Name Description

Pause the task while the trigger signal is high.


Pause the task while the trigger signal is low.


ready for transfer event active level

ready for transfer event active level specifies the polarity of the Ready for Transfer Event.

Name Description
Active High

Active high.

Active Low

Active low.


task out

task out is a reference to the task after this node runs.


error out

error out contains error information. If error in indicates that an error occurred before this node ran, error out contains the same error information. Otherwise, error out describes the error status that this node produces.

Where This Node Can Run:

Desktop OS: Windows

FPGA: LabVIEW NXG does not support FPGA devices

Web Server: Not supported in VIs that run in a web application

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