Table Of Contents

ni579x Host Driven Synchronization (G Dataflow)

Version:
    Last Modified: April 3, 2018

    Use this synchronization method in conjunction with ni579x FPGA Align on the FPGA to synchronize the FPGAs.

    Refer to the FPGA nodes for documentation.

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    Register Buses

    Specifies the Register Buses to which the Synchronization library is connected in the FPGA nodes.

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    error in

    Error conditions that occur before this node runs.

    The node responds to this input according to standard error behavior.

    Standard Error Behavior

    Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.

    error in does not contain an error error in contains an error
    If no error occurred before the node runs, the node begins execution normally.

    If no error occurs while the node runs, it returns no error. If an error does occur while the node runs, it returns that error information as error out.

    If an error occurred before the node runs, the node does not execute. Instead, it returns the error in value as error out.

    Default: No error

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    sync.cptr.period

    The period, in clocks, of the Common Periodic Time Reference (CPTR). The CPTR period controls the rate at which synchronized signals are realized. This parameter is required, and you must specify a value for each target to be synchronized. When using ni579x FPGA Align, the CPTR period must be the same as the Reference Clock period. The sync.cptr.period must be set to the ratio of the clock-driven logic (CDL) rate (that the Align node is in) to the sync.meas.Reference Clock rate. For example, the CPTR period must be 13 if you are using PXI_Clk10 for the Reference Clock, and the IO Module\Sample Clock for the CDL clock (130 MHz / 10 MHz). When using ni579x Host Align, this value is configurable. The maximum value is 63. The minimum value for sync.cptr.period must be large enough to ensure transmission across the sync.cptr.FPGA I/O line. Refer to the specifications for the FPGA I/O line that you choose. For example, if the FPGA I/O line has a maximum propagation delay of 50 ns, the minimum value is 7 (the period of the 130 MHz IO Module\Sample Clock is approximately 7.692 ns, so 7 clocks are required to exceed 50 ns). NI does not recommend changing the CPTR period on-the-fly. Alignment must be re-run if you change the CPTR period.

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    Register Buses (out)

    Passes the Register Buses to the next node.

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    error out

    Error information.

    The node produces this output according to standard error behavior.

    Standard Error Behavior

    Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.

    error in does not contain an error error in contains an error
    If no error occurred before the node runs, the node begins execution normally.

    If no error occurs while the node runs, it returns no error. If an error does occur while the node runs, it returns that error information as error out.

    If an error occurred before the node runs, the node does not execute. Instead, it returns the error in value as error out.

    Where This Node Can Run:

    Desktop OS: Windows

    FPGA: Not supported

    Web Server: Not supported in VIs that run in a web application


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