Synchronously realizes a signal.
If this target is the master, it distributes
on the specified FPGA I/O line on the next falling edge of the CPTR when
is high. If this target is not the master, it ignores
. All targets also read the FPGA I/O line. The
output goes high on the next CPTR edge after the edge is read from the FPGA I/O line.
input should be a pulse. This is enforced by the node. The
input contains a rising edge detector. After an edge is detected, another edge is not recognized until after the edge distribution has completed. Therefore, the minimum time between edges for synchronization is one to two CPTR periods, depending on when the edge is detected within the CPTR period.
Identifies the Synchronization instance.
is obtained from
The FPGA I/O line that distributes/reads the
for synchronization. This signal is commonly a PXI trigger line.
For large NI chassis, ensure the same PXI trigger line is routed to all bus segments that have targets participating in synchronization.
Specifies whether to synchronize the input
is a PXI trigger line, it will be floating until a target is specified as the master. The
parameter should be FALSE until after the host Synchronization node executes in order to prevent erroneous outputs on
The input being synchronized. The first block this input encounters is a rising edge detector, so the input signal,
edge, is treated as a pulse.
Returns the number of clock cycles of delay that were added by synchronizing the input
edge. This value is zero if
is FALSE. If
is true, this value is only valid on the master target.
Returns the synchronized input edge if
is set to True.
is True, it's possible that
will be spuriously true before the host Synchronization nodes are run. NI recommends that you set
to False until after the host Synchronization node executes.
The synchronization instance is obtained from the create node.
Where This Node Can Run:
Desktop OS: none
Web Server: Not supported in VIs that run in a web application