Table Of Contents

ni579x Synchronize Signal (Clock-Driven Logic)

Version:
    Last Modified: August 4, 2018

    Synchronously realizes a signal.

    If this target is the master, it distributes edge on the specified FPGA I/O line on the next falling edge of the CPTR when edge is high. If this target is not the master, it ignores edge. All targets also read the FPGA I/O line. The synchronized edge output goes high on the next CPTR edge after the edge is read from the FPGA I/O line.
    spd-note-note
    Note

    The edge input should be a pulse. This is enforced by the node. The edge input contains a rising edge detector. After an edge is detected, another edge is not recognized until after the edge distribution has completed. Therefore, the minimum time between edges for synchronization is one to two CPTR periods, depending on when the edge is detected within the CPTR period.

    connector_pane_image
    datatype_icon

    sync.resources

    Identifies the Synchronization instance. Sync.resources is obtained from ni579x Create.

    datatype_icon

    sync.cptr.FPGA I/O

    The FPGA I/O line that distributes/reads the edge for synchronization. This signal is commonly a PXI trigger line.

    spd-note-note
    Note

    For large NI chassis, ensure the same PXI trigger line is routed to all bus segments that have targets participating in synchronization.

    datatype_icon

    enable

    Specifies whether to synchronize the input edge.

    spd-note-note
    Note

    If the sync.cptr.FPGA I/O is a PXI trigger line, it will be floating until a target is specified as the master. The enable parameter should be FALSE until after the host Synchronization node executes in order to prevent erroneous outputs on synchronized edge.

    datatype_icon

    edge

    The input being synchronized. The first block this input encounters is a rising edge detector, so the input signal, edge, is treated as a pulse.

    datatype_icon

    synchronization delay

    Returns the number of clock cycles of delay that were added by synchronizing the input edge. This value is zero if enable is FALSE. If enable is true, this value is only valid on the master target.

    datatype_icon

    synchronized edge

    Returns the synchronized input edge if enable is set to True.

    spd-note-note
    Note

    If enable is True, it's possible that synchronized edge will be spuriously true before the host Synchronization nodes are run. NI recommends that you set enable to False until after the host Synchronization node executes.

    datatype_icon

    sync.resources 2

    The synchronization instance is obtained from the create node.

    Where This Node Can Run:

    Desktop OS: none

    FPGA: Supported

    Web Server: Not supported in VIs that run in a web application


    Recently Viewed Topics