# MT Phase Locked Loop (MT Passband PLL) (G Dataflow)

Version:

Simulates the operation of the phase-locked loop (PLL) in response to an input real passband waveform that has an unknown phase and frequency offset.

This node attempts to track the unknown phase of an input complex exponential tone by means of a feedback control system. At steady state, when the PLL has acquired a lock to the input signal, the PLL estimates the offset of the input signal carrier phase and carrier frequency from the reference phase and frequency. The passband waveform is assumed to consist of a tone at a user-specified nominal carrier phase and frequency, which is used as a reference to the PLL. The PLL is a feedback control system that employs a phase detector, loop filter, and a voltage-controlled oscillator (VCO) for its operation. The PLL tracks the instantaneous phase and frequency of the input waveform and returns an estimate of the carrier phase and frequency. You can use these estimates to adjust or correct the phase of the input waveform (for example, carrier phase or frequency offset correction in M-ary PSK digital communication systems).

## passband waveform

A passband waveform comprising of a tone at the carrier, with a frequency and phase that are to be estimated by the PLL.

## VCO carrier frequency

The reference carrier frequency, in Hertz (Hz), which is used by the VCO to track the carrier phase of the input signal.

Default: 0

## VCO initial phase

The reference initial carrier phase, in degrees, which is used by the VCO to track the carrier phase of the input signal.

Default: 0

## VCO gain

The gain applied to the error signal inside the VCO before generating the estimated initial phase parameter.

Default: 1

## error in

Error conditions that occur before this node runs.

The node responds to this input according to standard error behavior.

Standard Error Behavior

Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.

error in does not contain an error error in contains an error
If no error occurred before the node runs, the node begins execution normally.

If no error occurs while the node runs, it returns no error. If an error does occur while the node runs, it returns that error information as error out.

If an error occurred before the node runs, the node does not execute. Instead, it returns the error in value as error out.

Default: No error

## loop filter reverse coefficients

The reverse coefficients of the IIR loop filter.

Default: (1 -1)

## loop filter forward coefficients

The forward coefficients of the IIR loop filter.

Default: (1.05 -0.95)

## reset ?

A Boolean that determines whether to clear the internal state of the PLL prior to starting operation.

 TRUE Clears all state information, and initializes the PLL with the initial phase given in the PLL settings cluster. FALSE Uses the state information at the end of the previous iteration to initialize the PLL at the beginning of the current iteration.

Default: TRUE

## VCO phase

The overall phase of the input signal estimated by the PLL, including the effects of any carrier phase and frequency offsets.

## phase error

The carrier phase error signal at the phase detector output inside the PLL. You can use this value to estimate the phase difference between the input signal and the regenerated phase at the PLL output. When the PLL locks, phase error values approach zero.

## estimated carrier frequency

The actual carrier frequency of the input signal, as estimated by the PLL, accounting for any carrier frequency offset. Use the difference between the estimated carrier frequency and the nominal input carrier frequency to estimate the carrier frequency offset.

## estimated initial phase

The actual carrier phase of the input signal, as estimated by the PLL, with respect to the specified nominal carrier phase. Use the difference between the estimated carrier phase and the input nominal carrier phase to estimate the scalar carrier phase offset.

## error out

Error information.

The node produces this output according to standard error behavior.

Standard Error Behavior

Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.

error in does not contain an error error in contains an error
If no error occurred before the node runs, the node begins execution normally.

If no error occurs while the node runs, it returns no error. If an error does occur while the node runs, it returns that error information as error out.

If an error occurred before the node runs, the node does not execute. Instead, it returns the error in value as error out.

## Phase-Locked Loop Elements

The PLL nodes are continuable, meaning that you can successively send a phase-continuous signal to the node over multiple iterations when reset? is set to FALSE. A PLL contains three basic elements:

• Phase detector
• IIR loop filter
• Voltage controlled oscillator (VCO)
The phase detector block measures the approximate error between the estimated phase and the actual phase of the incoming signal. The IIR loop filter block then filters out any high-frequency noise present in the error signal and helps tracking phase and frequency offset errors. A first-order lowpass filter block tracks an initial phase offset, but returns a constant phase offset in the presence of a frequency offset. Higher-order filters track both phase and frequency offsets at steady state, as summarized in the following table.
1 1 (Order I) Tracks frequency error, steady state phase offset
$1+\frac{a}{s}$ $\frac{\left(0.5a+1\right)+\left(0.5a-1\right){z}^{-2}}{1-{z}^{-1}}$ (Order II) Tracks phase and frequency error, not offset
$\frac{s+a}{s+\epsilon }$ $M\frac{1-\left(\frac{2-a}{2+a}\right){z}^{-1}}{1-\left(\frac{2-\epsilon }{2+\epsilon }\right){z}^{-1}}$ (Order II) Tracks phase and frequency error, not offset
$1+\frac{a}{s}+\frac{b}{{s}^{2}}$ $\frac{\left(4+2a+b\right)+\left(2b-8\right){z}^{-1}+\left(b-2a+4\right){z}^{-2}}{4\left(1-2{z}^{-1}+{z}^{-2}\right)}$ (Order III) Tracks phase and frequency error, not offset

Where This Node Can Run:

Desktop OS: Windows

FPGA: Not supported

Web Server: Not supported in VIs that run in a web application