Communicates to the host VI that a specific interrupt occurred.
This node asserts an interrupt on the interrupt line of the FPGA target. Since this node is a shared resource, multiple uses of it induce additional delay and jitter due to arbitration. To handle the interrupts in the host VI, use the Wait on Interrupt(s) and Acknowledge Interrupt(s) nodes.
Number that specifies which interrupt to assert.
Typical supported values are 0 through 31 unless the target documentation specifies otherwise.
Where This Node Can Run:
Desktop OS: Windows
FPGA: All devices
Web Server: Not supported in VIs that run in a web application