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Decimate 1D Array (G Dataflow)

Last Modified: January 12, 2018

Divides the elements of an array into multiple output arrays, placing elements into the outputs successively.

This node drops any elements that cause the output arrays to have different lengths.



A 1D array of any type.

Data Type Changes on FPGA

When you add this node to a document targeted to an FPGA, this input has a default data type that uses fewer hardware resources at compile time.


decimated array

The node stores array[0] at index 0 of the first output array, array[1] is stored at index 0 of the second output array, array[n-1] at index 0 of the last output array, array[n] at index 1 of the first output array, and so on, where n is the number of output terminals for this node.

The following table demonstrates how the behavior of Decimate 1D Array varies depending on whether the input array is evenly divisible between outputs.
array input decimated array 1 decimated array 2 decimated array 3 decimated array 4 Comments
1D array with 16 elements numbered 0 to 15 {0,4,8,12} {1,5,9,13} {2,6,10,14} {3,7,11,15} Decimate 1D Array divides the array input between all decimated array outputs, element-by-element.
1D array with 15 elements numbered 0 to 14 {0,4,8} {1,5,9} {2,6,10} {3,7,11} Because Decimate 1D Array only returns arrays of the same size, all decimated array outputs drop the last element so that all of the arrays contain 3 elements.

Where This Node Can Run:

Desktop OS: Windows

FPGA: All devices (only within an optimized FPGA VI)

Web Server: Supported in VIs that run in a web application

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