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In Range and Coerce (G Dataflow)

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Last Modified: January 12, 2018

Determines whether the input value falls within a range specified by the upper and lower limits and optionally coerces the value to fall within the range.

To allow the node to perform coercion, select Elements in the Behavior section of the Item tab.

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upper limit

The upper limit of the range.

Data Type Changes on FPGA

When you add this node to a document targeted to an FPGA, this input has a default data type that uses fewer hardware resources at compile time.

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x

The value to test in the range and optionally coerce if it does not fall between the upper and lower limits. This input changes to waveform when the data type is a waveform.

This input supports all data types.

Data Type Changes on FPGA

When you add this node to a document targeted to an FPGA, this output has a default data type that uses fewer hardware resources at compile time.

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lower limit

The lower limit of the range.

Data Type Changes on FPGA

When you add this node to a document targeted to an FPGA, this input has a default data type that uses fewer hardware resources at compile time.

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in range?

A Boolean value that indicates whether the input value is in range.

True x is in range.
False x is out of range. This node also returns False if x, upper limit, or lower limit is NaN.

In Compare Elements mode, the data type structure of in range? matches the data type structure of x, with each scalar replaced by a Boolean value.

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coerced

The coerced or unchanged input value.

Comparison Modes and x Value Behavior

If x is within the range set by the upper limit and lower limit or if the node is in Compare Aggregates mode, the value is unchanged. If x is not in range and the node is in Compare Elements mode, the node converts the value to the same value as upper limit or lower limit. If upper limit, x, or lower limit is NaN, coerced is NaN.

Data Type Changes on FPGA

When you add this node to a document targeted to an FPGA, this output has a default data type that uses fewer hardware resources at compile time.

Where This Node Can Run:

Desktop OS: Windows

FPGA: This product does not support FPGA devices

Web Server: Supported in VIs that run in a web application

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