Specifies a maximum rate of change of a signal.
A Boolean or a Boolean array that determines whether to use initial output to compute the rate limiter.
True | Uses initial output to compute the rate limiter. |
False | Uses the previous output to compute the rate limiter. |
This node automatically uses initial output to compute the rate limiter on the first call.
Default: False
Input signal.
This input accepts a double-precision, floating-point number or an array of double-precision, floating-point numbers.
Allowable positive change in the output signal between successive calls to this node.
This input accepts a double-precision, floating-point number or an array of double-precision, floating-point numbers.
Default: 0
Allowable negative change in the output signal between successive calls to this node.
This input accepts a double-precision, floating-point number or an array of double-precision, floating-point numbers.
Default: 0
Output value on the first call to this node or when reset is True.
This input accepts a double-precision, floating-point number or an array of double-precision, floating-point numbers.
Default: 0
Loop-cycle time or interval, in seconds, at which this node is called.
dt must be greater than zero.
Output signal.
This output can return a double-precision, floating-point number or an array of double-precision, floating-point numbers.
The following equations define the rate limiter function.
where
Where This Node Can Run:
Desktop OS: Windows
FPGA: This product does not support FPGA devices