Table Of Contents

PDM Acquisition Toolkit Specifications for PXIe-7820R/7821R

Version:
Last Modified: March 31, 2021

Refer to these specifications when using the LabVIEW PDM Acquisition Toolkit with the PXIe-7820R/7821R.

Input Characteristics

  Acquisition Generation
Number of PDM data lines 32, consisting of four banks of 8 data lines and 2 clock lines 16
Number of PDM channels 64, consisting of four banks of 16 channels 32
Number of timing engines 2 1
Clock input/output Clock output—One master bit clock shared across 8 data lines (16 channels) Clock input—One input shared across all output channels
Data, clock, and GPIO logical level Single-ended logic 1.2 V, 1.8 V, and 3.3 V Single-ended logic 1.2 V, 1.8 V, and 3.3 V
PDM clock rate 10 to 4800 kb/s, master mode only 10 to 4800 kb/s, slave mode only
Timebase reference source PXI Express 100 MHz N/A
Timebase accuracy error
Divided clock <2%, 250 ps peak-peak jitter N/A
DDS clock <100 ppm, 8.3 ns peak-peak jitter N/A
Phase/Synchronization All channels within a bank of 8 data lines are sampled synchronously from a common clock. Phase relationship between channels is fully maintained. Channels within a task are synchronized. All channels are generated synchronously from the input clock. Phase relationship between channels is fully maintained.
Generation signal types N/A Sine, chirp (linear or logarithmic), white noise, and custom periodic signals
General purpose digital I/O (GPIO) 24 static GPIO lines can be configured independently as input or output lines 8 static GPIO lines can be configured independently as input or output lines

Refer to the Bank to Channel Mapping for PXIe-7820R/7821R for the layout of banks, data lines, channels, and clock lines.

Decimation Filters

Decimation factor options 24, 32, 48, 64, 96, and 128. Select the option by task.

Decimation Filter Specifications

Decimation Factor 24 and 48 32 and 64 96 and 128
Normalized passband frequency 0.4275 0.438 0.45
Passband ripple (dB) ±0.0025 ±0.001 ±0.0004
Normalized stopband frequency 0.5725 0.562 0.55
Stopband attenuation (dB) >110 >120 >123
Filter output delay (samples) 23 30 38

Acquisition and Generation Control

  Acquisition Generation
Acquisition options Raw PDM and/or PCM (decimated) data N/A
Acquisition/Generation mode Finite or Continuous Continuous
Trigger options Immediate or PXI-Trigger. Independent triggering on each task Immediate or PXI-Trigger
Export signal options N/A Start trigger to a PXI trigger line
PXI trigger PXI-Trig [0..7]. Rising or Falling edge PXI-Trig [0..7]. Rising or Falling edge
Acquisition pre-delay Common pre-delay for each task applied to both PDM and PCM data N/A
Acquisition pre-delay resolution 1 PDM bitrate period N/A
Acquisition pre-delay range 0 to 16383 bitrate periods N/A
Acquisition post-delay Common post-delay for each task and applied to decimated data N/A
Acquisition post-delay resolution 1 decimated data period N/A
Acquisition post-delay range 0 to 227-2 (134,217,726) decimated data periods N/A

Simulation Mode

PDM simulation signal type Sine tone with a PDM amplitude of ±0.7071 FS (0.500 RMS)
Tone frequency Proportional to the selected PDM rate and repeats for every group of 16 PDM channel inputs.
For a PDM rate of 3.072 MHz, tone frequency is 1 kHz for the first PDM channel input, increments by 1 kHz for each PDM channel input, and repeats this sequence for every 16 PDM channel inputs. The following table illustrates the tone frequencies at 3.072 MHz for all 64 PDM channel inputs.
PDM Channel Input 0L 1 kHz
PDM Channel Input 0R 2 kHz
...  
PDM Channel Input 7L 15 kHz
PDM Channel Input 7R 16 kHz
PDM Channel Input 8L 1 kHz
PDM Channel Input 8R 2 kHz
...  
PDM Channel Input 31L 15 kHz
PDM Channel Input 31R 16 kHz

Refer to the Bank to Channel Mapping for PXIe-7820R/7821R for the layout of banks, data lines, channels, and clock lines.

Tone start phase 0 degree for all tones when using the Configure PDM Trigger (None) VI

Bank to Channel Mapping for PXIe-7820R/7821R

The following table illustrates the bank to channel mapping for the PXIe-7820R/7821R.

Bank 0 PDM Data Input 0 PDM Channel Input 0L   Bank 2 PDM Data Input 16 PDM Channel Input 16L
PDM Channel Input 0R PDM Channel Input 16R
... . ... .
. .
. .
PDM Data Input 7 PDM Channel Input 7L PDM Data Input 23 PDM Channel Input 23L
PDM Channel Input 7R PDM Channel Input 23R
Clock 0,1 Clock 4,5
Bank 1 PDM Data Input 8 PDM Channel Input 8L Bank 3 PDM Data Input 24 PDM Channel Input 24L
PDM Channel Input 8R PDM Channel Input 24R
... . ... .
. .
. .
PDM Data Input 15 PDM Channel Input 15L PDM Data Input 31 PDM Channel Input 31L
PDM Channel Input 15R PDM Channel Input 31R
Clock 2,3 Clock 6,7

Connector Pin Assignments for PXIe-7820R/7821R PDM Acquisition

Use the following connector pin assignments when you configure pin functions for PDM acquisition using the PXIe-7820R/7821R.

Connector 0

Terminal Function Assignment
1 DIO31 PDM Input 15
2 GND  
3 DIO29 GPIO 11
4 GND  
5 DIO27 GPIO 9
6 GND  
7 DIO25 PDM Input 13
8 GND  
9 DIO23 PDM Input 11
10 GND  
11 DIO21 PDM Input 9
12 GND  
13 DIO19 PDM Clock Output 3
14 GND  
15 DIO17 GPIO 7
16 GND  
17 DIO15 GPIO 5
18 GND  
19 DIO13 PDM Clock Output 1
20 GND  
21 DIO11 PDM Input 7
22 GND  
23 DIO9 PDM Input 5
24 GND  
25 DIO7 PDM Input 3
26 GND  
27 DIO5 GPIO 3
28 GND  
29 DIO3 GPIO 1
30 GND  
31 DIO1 PDM Input 1
32 GND  
33 GND
34 GND
35 DIO30 PDM Clock Output 2
36 GND
37 DIO28 PDM Input 14
38 GND
39 DIO26 PDM Input 12
40 GND
41 DIO24 PDM Input 10
42 GND
43 DIO22 GPIO 10
44 GND
45 DIO20 GPIO 8
46 GND
47 DIO18 GPIO 6
48 GND
49 DIO16 PDM Input 8
50 GND
51 DIO14 PDM Input 6
52 GND
53 DIO12 GPIO 4
54 GND
55 DIO10 GPIO 2
56 GND
57 DIO8 GPIO 0
58 GND
59 DIO6 PDM Input 4
60 GND
61 DIO4 PDM Input 2
62 GND
63 DIO2 PDM Input 0
64 GND
65 DIO0 PDM Clock Output 0
66 GND
67 External Clock x*
68 GND
* x is the connector number. External Clock x is an input only.

Connector 1

Terminal Function Assignment
1 DIO31 PDM Input 31
2 GND
3 DIO29 GPIO 23
4 GND
5 DIO27 GPIO 21
6 GND
7 DIO25 PDM Input 29
8 GND
9 DIO23 PDM Input 27
10 GND
11 DIO21 PDM Input 25
12 GND
13 DIO19 PDM Clock Output 7
14 GND
15 DIO17 GPIO 19
16 GND
17 DIO15 GPIO 17
18 GND
19 DIO13 PDM Clock Output 5
20 GND
21 DIO11 PDM Input 23
22 GND
23 DIO9 PDM Input 21
24 GND
25 DIO7 PDM Input 19
26 GND
27 DIO5 GPIO 15
28 GND
29 DIO3 GPIO 13
30 GND
31 DIO1 PDM Input 17
32 GND
33 GND
34 GND
35 DIO30 PDM Clock Output 6
36 GND
37 DIO28 PDM Input 30
38 GND
39 DIO26 PDM Input 28
40 GND
41 DIO24 PDM Input 26
42 GND
43 DIO22 GPIO 22
44 GND
45 DIO20 GPIO 20
46 GND
47 DIO18 GPIO 18
48 GND
49 DIO16 PDM Input 24
50 GND
51 DIO14 PDM Input 22
52 GND
53 DIO12 GPIO 16
54 GND
55 DIO10 GPIO 14
56 GND
57 DIO8 GPIO 12
58 GND
59 DIO6 PDM Input 20
60 GND
61 DIO4 PDM Input 18
62 GND
63 DIO2 PDM Input 16
64 GND
65 DIO0 PDM Clock Output 4
66 GND
67 External Clock x*
68 GND
* x is the connector number. External Clock x is an input only.

Connector Pin Assignments for PXIe-7820R/7821R PDM Generation

Use the following connector pin assignments when you configure pin functions for PDM generation using the PXIe-7820R/7821R.

Connector 0

Terminal Function Assignment
1 DIO31 PDM Output 15
2 GND  
3 DIO29  
4 GND  
5 DIO27  
6 GND  
7 DIO25 PDM Output 13
8 GND  
9 DIO23 PDM Output 11
10 GND  
11 DIO21 PDM Output 9
12 GND  
13 DIO19  
14 GND  
15 DIO17 GPIO 7
16 GND  
17 DIO15 GPIO 5
18 GND  
19 DIO13  
20 GND  
21 DIO11 PDM Output 7
22 GND  
23 DIO9 PDM Output 5
24 GND  
25 DIO7 PDM Output 3
26 GND  
27 DIO5 GPIO 3
28 GND  
29 DIO3 GPIO 1
30 GND  
31 DIO1 PDM Output 1
32 GND  
33 GND
34 GND
35 DIO30  
36 GND
37 DIO28 PDM Output 14
38 GND
39 DIO26 PDM Output 12
40 GND
41 DIO24 PDM Output 10
42 GND
43 DIO22  
44 GND
45 DIO20  
46 GND
47 DIO18 GPIO 6
48 GND
49 DIO16 PDM Output 8
50 GND
51 DIO14 PDM Output 6
52 GND
53 DIO12 GPIO 4
54 GND
55 DIO10 GPIO 2
56 GND
57 DIO8 GPIO 0
58 GND
59 DIO6 PDM Output 4
60 GND
61 DIO4 PDM Output 2
62 GND
63 DIO2 PDM Output 0
64 GND
65 DIO0 PDM Clock 0
66 GND
67 External Clock x*
68 GND
* x is the connector number. External Clock x is an input only.

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